comp.lang.SystemVerilog ???

[Jonathan Bromley]

SystemVerilog is very much here, possibly here to stay...
do we need a new comp.lang.systemverilog, or do we simply
use this group?

And what do we infer from the fact that there is very
little SystemVerilog-related traffic here?

Looking forward to all your insights.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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[Neo]

In my opinion it would be better to continue using this group for SV as
well since it is the same language with added features and
improvements. It will also enable people using verilog see how SV is
handling some of the verilog features and who knows, they might
consider a switch.
The only reason that I can make out for very less SV related queries is
that its still not become part of the regular design flow for many
companies. And that may also be beacuse of tool support for SV.

 

Maybe it reflects the fact that most simulation products with full
SystemVerilog support are much more expensive than those that just do
Verilog 2001 and VHDL.