Communication between modules, ports and memories

[Marwan]

Peace,

These are simple question for a person who knows to answer no
doubt... But questions that are seemingly rarely asked or answered in
a clear manner...

So here they are for any future searchers of this group:-

--> How can the output and input ports of a module be used/referenced/
driven by any other module in a design?
------> Do both modules have to be instantiated within some higher
level module?
------> Can the port names of one module (A) (example: data_in_A)
just be used in another module (B) in its port list so that it can
communicate with (A)?

--> If a memory is defined in module (A) (i.e., reg [4:0] mem1 [0:6]
[0:6]), can it be directly used in module (B) by just writing out =
mem1[1][2]; ?
------> This answer will no doubt be tied to the answer(s) for above.

Thank you in advance for any help.

Peace.

 

[Marwan]

Just to make sure the questions are clear...

Q1: How can the output and input ports of a module be used/
referenced/
driven by any other module in a design (I want to make the outputs of
one module the inputs in another module)?
Q1.1: Do both modules have to be instantiated within some higher
level module (module top (module A, module B))?
Q1.2: Can the port names of one module (A) (example: data_in_A)
just be used in another module (B) in its port list so that it can
communicate with (A)?

Q2: If a memory is defined in module (A) (i.e., reg [4:0] mem1 [0:6]
[0:6]), can it be directly used in module (B) by just writing "out =
mem1[1][2];" ?

This answer will no doubt be tied to the answer(s) for Q1 for above.

 

[Andy Peters]

On Aug 2, 12:15 pm, Marwan <marwanboust...@gmail.com> wrote:

Just to make sure the questions are clear...

Q1: How can the output and input ports of a module be used/
referenced/
driven by any other module in a design (I want to make the outputs of
one module the inputs in another module)?
Q1.1: Do both modules have to be instantiated within some higher
level module (module top (module A, module B))?

Yes, if you need to have module A talk to module B, both must be
instantiated in a higher-level module.

Q1.2: Can the port names of one module (A) (example: data_in_A)
just be used in another module (B) in its port list so that it can
communicate with (A)?

In your higher-level module (the one that instantiates A and B), you
will need to declare wires that you'll use on each module's ports.

[0:6]), can it be directly used in module (B) by just writing "out =
mem1[1][2];" ?

You'll have to define ports for whatever you wish to bring out of
module B.

-a