common dataflow tree for verilog and vhdl

[Nikhil Patil]

Hi,

I am trying to write a tool that shall process synthesizable HDL. I
wish to do this in a way such that I can support both Verilog and VHDL
without too much extra effort. (I don't really care about the
simulation specific syntactic structures of the languages, the
synthesizable subset is good enough.)

Does anybody know of any good open-source parsers for verilog and vhdl
that produce a common dataflow tree, that I might use as my starting
point?

Thanks.
Nikhil