Comments in PSL

[dbwalker0min@gmail.com]

Does anyone know of a clever way to add comments in PSL embedded in
Verilog?

David Walker

 

[Ajeetha (www.noveldv.com)]

On Jan 30, 8:36 am, "dbwalker0...@gmail.com" <dbwalker0...@gmail.com>
wrote:

Does anyone know of a clever way to add comments in PSL embedded in
Verilog?

David Walker

David,
Sorry if I didn't get your question correctly, but PSL supports
commenting as per the underlying flavor - so in Verilog, regular

// comment here

should work. See my PSL tutorial at www.project-veripage.com,
specifically

http://www.project-veripage.com/psl_tutorial_8.php

HTH
Ajeetha, CVC
www.noveldv.com

 

[dbwalker0min@gmail.com]

Hmmm...

That didn't work for me. Take the following PSL assertion...

// psl my_sequence: assert always
// (sstb -> {
// [*0:1] ;
// (xswitch && iqp == 47)[*62:63] ;
// (xswitch && iqp == 18)[*26:27] ;
// (!xswitch && (pll_lo_rx && (iqp == 1) ||
// pll_lo_tx && (iqp == 1 +
current_registers.iqpadj)))})
// @(posedge t.sstb or posedge tclk100);

I want to be able to add comments to this. If I follow your advice, I
would do something like...

// psl my_sequence: assert always
// (sstb -> {
// [*0:1] ; //
synchronizer delay
// (xswitch && iqp == 47)[*62:63] ; // first stage
// (xswitch && iqp == 18)[*26:27] ; // second stage
// (!xswitch && (pll_lo_rx && (iqp == 1) ||
// pll_lo_tx && (iqp == 1 +
current_registers.iqpadj)))}) // final stage
// @(posedge t.sstb or posedge tclk100);

However, the nested comments give syntax errors in my tool (nc-
Verilog). So apparently you can't embed comments within the comments.

David Walker

On Jan 29, 10:14 pm, "Ajeetha (www.noveldv.com)" <ajee...@gmail.com>
wrote:

On Jan 30, 8:36 am, "dbwalker0...@gmail.com" <dbwalker0...@gmail.com
wrote:

Does anyone know of a clever way to add comments in PSL embedded in
Verilog?

David Walker

David,
Sorry if I didn't get your question correctly, but PSL supports
commenting as per the underlying flavor - so in Verilog, regular

// comment here

should work. See my PSL tutorial atwww.project-veripage.com,
specifically

http://www.project-veripage.com/psl_tutorial_8.php

HTH
Ajeetha, CVCwww.noveldv.com

 

dbwalker0min@gmail.com wrote:

Does anyone know of a clever way to add comments in PSL embedded in
Verilog?

Apparently you can do this with separate property files,
but not when the PSL is embedded in the Verilog code.

 

[Ajeetha (www.noveldv.com)]

David,

On Jan 30, 9:51 pm, "dbwalker0...@gmail.com" <dbwalker0...@gmail.com>
wrote:

Hmmm...

That didn't work for me. Take the following PSL assertion...

Similar stuff has worked for me in another simulator.

But as you may know, embedding of PSL into a HDL is/was not part of
LRM (atleast till the last time I checked). So I can imagine this
varying from vendor to vendor.

However, the nested comments give syntax errors in my tool (nc-
Verilog). So apparently you can't embed comments within the comments.

I would recommend you to file an enhancement request with Cadence in
this case.

HTH
Ajeetha, CVC
www.noveldv.com