C
Chris Carlen
Guest
Greetings:
I am learning Verilog from the book "A Verilog Primer 2nd. ed." by J.
Bhasker.
Here's my crack at a digital one shot. It works fine, or course, since
I have already used it in real hardware. But I am interested in
pointers on coding style or any other comments people might like to make:
Note: some of the delays and the initial statement are for making the
functional simulation work, but I know they get ignored during synthesis.
----------------------------------------------------------
/* This module implements a digital one-shot with N-bit resolution.
Ports:
Trig_in rising edge causes output pulse to begin
Out positive going output pulse appears here
Clk_in user must supply a clock here
Delay user must supply an N-bit value here for the number of
clock periods to delay
How it works:
An N-bit counter gets clocked all the time by the incoming clock signal.
A D-flop latches the input trigger and also enables the counter. The
output pulse is taken from the D-flop Q output. Thus the leading edge
of the output pulse is synchronous with the trigger edge. But the
trailing edge of the output will be synchronous with the clock.
At the end of a delay cycle, the D-flop Q output falls and resets the
counter, preparing it to count again. An incoming trigger pulse sets
the D-flop, causing Q to rise, releasing the CLR of the counter. When
the count reaches the Delay value, the D-flop is reset. This causes the
Q to fall again, clearing and holding the counter until the next trigger.
*/
module DelayNbit(Trig_in, Out, Clk_in, Delay);
parameter NUM_BITS = 8; // This sets the default number of bits of
counter resolution
input Trig_in, Clk_in;
input [NUM_BITS-1:0] Delay;
output Out;
wire Trig_in, Clk_in;
wire [NUM_BITS-1:0] Delay;
reg Out;
wire Clr_ff; // flip-flop asynchronous clear input
reg [NUM_BITS-1:0] Q_c; // register for N-bit counter
/* BEGIN behavioral model of the D flip-flop with asynchronous clear,
adapted from Xilinx <lib.pdf>:
*/
initial
Out = 0;
always @ ( posedge Trig_in or posedge Clr_ff )
begin
if ( Clr_ff == 1 )
#4 Out <= 0;
else
#4 Out <= 1; // we tie the D input to logical high
end
// END of D flip-flop behavioral model
/* BEGIN behavioral model of N-bit counter with asynchronous clear,
adapted from Xilinx <lib.pdf> :
*/
always @ ( posedge Clk_in or negedge Out )
begin
if ( !Out )
#4 Q_c <= 0;
else
#4 Q_c <= Q_c + 1;
end
// END of N-bit counter behavioral model
assign #4 Clr_ff = ( Q_c == Delay ); /* this compares the count with
Delay, and when equal
resets the flip-flop. */
endmodule
----------------------------------------------------------
Thanks for input.
Good day!
--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov
I am learning Verilog from the book "A Verilog Primer 2nd. ed." by J.
Bhasker.
Here's my crack at a digital one shot. It works fine, or course, since
I have already used it in real hardware. But I am interested in
pointers on coding style or any other comments people might like to make:
Note: some of the delays and the initial statement are for making the
functional simulation work, but I know they get ignored during synthesis.
----------------------------------------------------------
/* This module implements a digital one-shot with N-bit resolution.
Ports:
Trig_in rising edge causes output pulse to begin
Out positive going output pulse appears here
Clk_in user must supply a clock here
Delay user must supply an N-bit value here for the number of
clock periods to delay
How it works:
An N-bit counter gets clocked all the time by the incoming clock signal.
A D-flop latches the input trigger and also enables the counter. The
output pulse is taken from the D-flop Q output. Thus the leading edge
of the output pulse is synchronous with the trigger edge. But the
trailing edge of the output will be synchronous with the clock.
At the end of a delay cycle, the D-flop Q output falls and resets the
counter, preparing it to count again. An incoming trigger pulse sets
the D-flop, causing Q to rise, releasing the CLR of the counter. When
the count reaches the Delay value, the D-flop is reset. This causes the
Q to fall again, clearing and holding the counter until the next trigger.
*/
module DelayNbit(Trig_in, Out, Clk_in, Delay);
parameter NUM_BITS = 8; // This sets the default number of bits of
counter resolution
input Trig_in, Clk_in;
input [NUM_BITS-1:0] Delay;
output Out;
wire Trig_in, Clk_in;
wire [NUM_BITS-1:0] Delay;
reg Out;
wire Clr_ff; // flip-flop asynchronous clear input
reg [NUM_BITS-1:0] Q_c; // register for N-bit counter
/* BEGIN behavioral model of the D flip-flop with asynchronous clear,
adapted from Xilinx <lib.pdf>:
*/
initial
Out = 0;
always @ ( posedge Trig_in or posedge Clr_ff )
begin
if ( Clr_ff == 1 )
#4 Out <= 0;
else
#4 Out <= 1; // we tie the D input to logical high
end
// END of D flip-flop behavioral model
/* BEGIN behavioral model of N-bit counter with asynchronous clear,
adapted from Xilinx <lib.pdf> :
*/
always @ ( posedge Clk_in or negedge Out )
begin
if ( !Out )
#4 Q_c <= 0;
else
#4 Q_c <= Q_c + 1;
end
// END of N-bit counter behavioral model
assign #4 Clr_ff = ( Q_c == Delay ); /* this compares the count with
Delay, and when equal
resets the flip-flop. */
endmodule
----------------------------------------------------------
Thanks for input.
Good day!
--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov