Combining resistors from different technologies

[Dmitriy Shurin]

Hey,we took resistor cells from Tsmc18rf kit however the layout was done
in cmosp18 technology ,we changed divaextract file so they passed lvs
and in the extracted file l,w,r were the same as in the schematic file ,
however in the final post layout simulation the result are extremely
different the netlist of the layout shows different value of length and
width and therefore the resistance different also ,is there anything we
can do about it
Thanks


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[fogh]

Dmitriy Shurin wrote:

Hey,we took resistor cells from Tsmc18rf kit however the layout was done
in cmosp18 technology ,we changed divaextract file so they passed lvs
and in the extracted file l,w,r were the same as in the schematic file ,
however in the final post layout simulation the result are extremely
different the netlist of the layout shows different value of length and
width and therefore the resistance different also ,is there anything we
can do about it

You can not use a pcell from PDK of tech1 if you are taping out in tech2
It is technically a major annoyance, and is also illegal.

Also, a setup where you have multiple technology libraries (libs that have
their own techfile) is tricky. There are a number of parameters (such as layout
snapgrid) that are in an undefined state when you have that setup.

Why did you start with that resistor jamming anyway ? If you want a custom
resistor, you can better flatten a pcell of the tech you are really producing in
and customise that.