D
Dmitriy Shurin
Guest
we took resistors from tsmc18rf schematic cellview and we changed the
divaextract file of cmosp18 process so that in extracted view of the
layout the resistor had the same length width and resistance ,it also
passed lvs. However in the post layout simulation the results of the
schematic cell and the layout cell (amplifier) are totally different,
also the netlist of layout cell shows different values of length width
and therefore resistance,
Is there anything we can do about it??
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
divaextract file of cmosp18 process so that in extracted view of the
layout the resistor had the same length width and resistance ,it also
passed lvs. However in the post layout simulation the results of the
schematic cell and the layout cell (amplifier) are totally different,
also the netlist of layout cell shows different values of length width
and therefore resistance,
Is there anything we can do about it??
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG