combinational division

[krzyg]

Hi,
I have problem with sythesis. It says - division by not-constant signal
is not allowed.
Furthermore, divisor must be a power of 2. The same situation is when
using modulus operator.
How to divide two signals combinationally in below example?

process(clk)
begin
if clk = '1' and clk'event then
if s = '0' then
A <= A + X * Y;
B <= B + Y;
else
A <= X * Y;
B <= Y;
C <= A / B;
end if;
end if;
end process;

 

[Duane Clark]

krzyg wrote:

Hi,
I have problem with sythesis. It says - division by not-constant signal
is not allowed.
Furthermore, divisor must be a power of 2. The same situation is when
using modulus operator.
How to divide two signals combinationally in below example?

process(clk)
begin
if clk = '1' and clk'event then
if s = '0' then
A <= A + X * Y;
B <= B + Y;
else
A <= X * Y;
B <= Y;
C <= A / B;
end if;
end if;
end process;

You need to think hardware. How would the synthesis tool implement that
in hardware?

The answer is that no FPGAs (I assume that is what you are using) have
built in division. So you must implement it in logic, and likely it will
require multiple clocks and lots of circuitry. How you implement it
depends on the requirements of your system. There is no one size fits
all division. Problems like this are why you get paid the big bucks

 

[Rob Dekker]

"krzyg" <gientke@wp.pl> wrote in message news:deinhq$lij$1@nemesis.news.tpi.pl...

Hi,
I have problem with sythesis. It says - division by not-constant signal is not allowed.
Furthermore, divisor must be a power of 2. The same situation is when using modulus operator.
How to divide two signals combinationally in below example?

process(clk)
begin
if clk = '1' and clk'event then
if s = '0' then
A <= A + X * Y;
B <= B + Y;
else
A <= X * Y;
B <= Y;
C <= A / B;
end if;
end if;
end process;

The way you wrote it, the C signal divides the values
of A and B from the PREVIOUS clock cycle.
Is that intended ?

Even with that, it looks like A is always (at any clock cycle) X times larger than B,
so C will always be X (from the previous clock cycle).
Is that intended ? If so, write it like that, and no division is needed.

But I guess this is not your real design is it ?

 

[David Bishop]

krzyg wrote:

Hi,
I have problem with sythesis. It says - division by not-constant signal
is not allowed.
Furthermore, divisor must be a power of 2. The same situation is when
using modulus operator.
How to divide two signals combinationally in below example?

process(clk)
begin
if clk = '1' and clk'event then
if s = '0' then
A <= A + X * Y;
B <= B + Y;
else
A <= X * Y;
B <= Y;
C <= A / B;
end if;
end if;
end process;

First, Rob is right. This is equivalent to:
process (clk)
variable XY : unsigned(X'high+Y'high downto 0);
begin
if rising_edge(clk) then
XY := X * Y;
if s = '0' then
A <= A + XY;
B <= B + Y;
C <= C;
else
A <= XY;
C <= A / B;
B <= Y;
end if;
end if;
end process;

Next, division:

A divide can be done with subtracters, B'length + A'length + 3 of them.
Synplify and Synopsys can do it, but few other synthesis tools can.
You can also do a Newton Raphson reciprocal, which can be done with
multipliers. The secret code is:

q1 := q0*(2-a*q0);

Where "a" is this case is your variable "B". You can start with a seed,
which you can figure out by shifting "a" until you get it roughly to the
magnitude you need of the result that will become "q0". This link tells
you how it works:

http://numericalmethods.eng.usf.edu/mcd/com/03nle/mcd_com_nle_phy_problem.pdf

Figure about 8 multipliers (4 iterations) for a 16 bit number.

 

[krzyg]

Rob Dekker napisał(a):

"krzyg" <gientke@wp.pl> wrote in message news:deinhq$lij$1@nemesis.news.tpi.pl...

Hi,
I have problem with sythesis. It says - division by not-constant signal is not allowed.
Furthermore, divisor must be a power of 2. The same situation is when using modulus operator.
How to divide two signals combinationally in below example?

process(clk)
begin
if clk = '1' and clk'event then
if s = '0' then
A <= A + X * Y;
B <= B + Y;
else
A <= X * Y;
B <= Y;
C <= A / B;
end if;
end if;
end process;


The way you wrote it, the C signal divides the values
of A and B from the PREVIOUS clock cycle.
Is that intended ?

Even with that, it looks like A is always (at any clock cycle) X times larger than B,
so C will always be X (from the previous clock cycle).
Is that intended ? If so, write it like that, and no division is needed.

But I guess this is not your real design is it ?

Yeah, you're all right. It has to be written in different order:

C <= A / B;
A <= X * Y;
B <= Y;

First, C is evaluated, then A is set to X * Y [and B to Y].

But take a look: http://www.csee.umbc.edu/help/VHDL/samples/samples.shtml

It's parallel non-sequential divider, isn't it?

 

[Duane Clark]

krzyg wrote:

Yeah, you're all right. It has to be written in different order:

C <= A / B;
A <= X * Y;
B <= Y;

First, C is evaluated, then A is set to X * Y [and B to Y].

The order makes absolutely no difference.