combinational divider

[snehashis]

Hii friends,
I need a fully combinational divider circuit .Can anybody suggest a
pipelined one, comparable to wallace tree multiplier?

 

[John_H]

Please see my post in this newsgroup back on 10/22 regarding "ideas on
Divider design."

Are you a student? An FPGA or ASIC designer?
Do you know much or little?

Your requirements would help.

I realized, for instance, that a generic 8-bit numerator, 8-bit denominator
divider needs (both integers) needs 16 bits of fraction to have a unique
result to distinguish between 1/255 and 1/254. Do you want an integer and
remainder result instead of a binary fraction? Do you want rounding in your
design?

Look at my previous post and you'll see a simple scheme to cascade adders
for a combinatorial divide.


"snehashis" <snehashis_iitkgp@yahoo.co.in> wrote in message
news:f3e2968b78c8279747a2e39180209b39@localhost.talkaboutprogramming.com...

Hii friends,
I need a fully combinational divider circuit .Can anybody suggest a
pipelined one, comparable to wallace tree multiplier?

 

[glen herrmannsfeldt]

snehashis wrote:

I need a fully combinational divider circuit .Can anybody suggest a
pipelined one, comparable to wallace tree multiplier?

According to the definition of combinatorial that I am used to,
a pipelined design isn't combinatorial.

The question, then, is how many compare/subtract stages to put
between each pipeline register? That depends on the clock rate
and available logic family.

-- glen

 

[snehashis]

Thanks John and Glenn for your help.I should have been more specific.I need
a divider that divides 2 8 bit signed numbers and that gives only the
integer result as well as the integer remainder. I am a student doing
projects in FPGA design .I need the whole thing done in one clock cycle so
that in one cycle, divisor and dividend will give the output,this is only
to simplify some control unit.The post on 10/22 was very much
helpful,thanks for that.

 

[snehashis]

Thanks John and Glenn for your help.I should have been more specific.I need
a divider that divides 2 8 bit signed numbers and that gives only the
integer result as well as the integer remainder. I am a student doing
projects in FPGA design .I need the whole thing done in one clock cycle so
that in one cycle, divisor and dividend will give the output,this is only
to simplify some control unit.The post on 10/22 was very much
helpful,thanks for that.I appreciate any further help.

 

[John_H]

"Thomas Womack" <twomack@chiark.greenend.org.uk> wrote in message
news:f9y*vQ6xq@news.chiark.greenend.org.uk...
[snip]

What you are asking for is virtually impossible
[snip]

It's as "impossible" to build a divider as it is to build a multiplier from
a reqource perspective. Because the divider has to propagate through the
carry logic at each stage to decide what to do at the next stage, it just
takes longer. If someone is running from a 10 MHz clock, it's simple to
have a 16-bit divide in an FPGA - I think about 89 nS is what I showed on an
FPGA test compile. 8-bits is so very much easier.

 

[glen herrmannsfeldt]

Thomas Womack wrote:

(snip regarding a combinatorial 8 bit divider)

What you are asking for is virtually impossible; if you're using
something like a Stratix (EP1S20 or bigger) with its 512Kbit memory
blocks, you could use look-up tables, a 64k x 8 for each of result and
remainder, but otherwise it's an impractical random-logic problem.

If the clock cycle is really long you could build a shift-and-subtract
divider running at a much faster clock so it gets its work done in one
long-clock cycle, but getting the data across the clock boundary is
not completely straightforward.

For 8 bit I don't think it is all that hard to build a completely
combinatorial 8 bit divider. I will be a little big, but that
isn't all that hard to do these days. Eight stages of 8 bit compare
and 8 bit subtract. Quartus megafunction will generate one
in 97 logic cells and 42.21ns propagation delay.

-- glen

 

[Thomas Womack]

In article <c91ec9d716dd56ee718f001ec89db269@localhost.talkaboutprogramming.com>,
snehashis <snehashis_iitkgp@yahoo.co.in> wrote:

Thanks John and Glenn for your help.I should have been more specific.I need
a divider that divides 2 8 bit signed numbers and that gives only the
integer result as well as the integer remainder. I am a student doing
projects in FPGA design .I need the whole thing done in one clock cycle so
that in one cycle, divisor and dividend will give the output,this is only
to simplify some control unit.

What you are asking for is virtually impossible; if you're using
something like a Stratix (EP1S20 or bigger) with its 512Kbit memory
blocks, you could use look-up tables, a 64k x 8 for each of result and
remainder, but otherwise it's an impractical random-logic problem.

If the clock cycle is really long you could build a shift-and-subtract
divider running at a much faster clock so it gets its work done in one
long-clock cycle, but getting the data across the clock boundary is
not completely straightforward.

It would probably be easier to leave the control unit unsimplified.

Tom