Coding style

[Uwe Bonnes]

Recent version of Xilinx sythesis xst tool flag e.g. following code sample

reg [7:0] cnt;
always @(posedge clk)
cnt <= cnt +1,

with
WARNING:HDLCompiler:413 - "xxx" Line yyy: Result of 9-bit expression is
truncated to fit in 8-bit target.

You can silence the warning like

reg [7:0] cnt;
wire [8:0] adder = cnt + 1;
always @(posedge clk)
cnt <= adder[7:0];

Does the warning make sense? Does the effort to silence the warning make
sense? Any better way?

Thanks

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Stephen Williams]

Uwe Bonnes wrote:

Recent version of Xilinx sythesis xst tool flag e.g. following code sample

reg [7:0] cnt;
always @(posedge clk)
cnt <= cnt +1,

with
WARNING:HDLCompiler:413 - "xxx" Line yyy: Result of 9-bit expression is
truncated to fit in 8-bit target.

You can silence the warning like

reg [7:0] cnt;
wire [8:0] adder = cnt + 1;
always @(posedge clk)
cnt <= adder[7:0];

Try this: cnt <= cnt + 8'd1


--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Jonathan Bromley]

On May 6, 12:12 am, Uwe Bonnes wrote:

Recent version of Xilinx sythesis xst tool flag e.g. following code sample
reg [7:0] cnt;
always @(posedge clk)
   cnt <= cnt +1,
with
WARNING:HDLCompiler:413 - "xxx" Line yyy: Result of 9-bit expression is
truncated to fit in 8-bit target.

<snip>

Does the warning make sense?

It's odd, because the result is in fact 32 bits wide -
but of course XST knows that only the 9th bit can
hold useful information that may be lost.

It's also odd because it highlights a situation
where synthesis results correctly match simulation -
it's almost a lint-style check, warning you of
something that is processed correctly but you
might not have intended. Of course, in a
perfect world your simulation would already
have revealed that...

Consequently it pollutes the log file rather badly,
and may distract attention from more important
warnings that genuinely describe possible
mismatches between simulation and synthesis.

Does the effort to silence the warning make sense?

Perfectly, but I'm sure you'll agree it's extremely ugly.
It also involves assignment to signal adder[8] that
is never used, which might itself give rise to other
unwanted messages.

Any better way?

As an alternative to Stephen's suggestion, here's
another way to throw away the carry explicitly:

reg [7:0] cnt;
reg throwaway_carry;
always @(posedge clock)
{throwaway_carry, cnt} <= cnt + 1;

But that will probably yield warnings about register
'throwaway_carry' being stripped out...

If Stephen's suggestion of using a narrower addend
works, you can make it more flexible like this:

cnt <= cnt + 1'b1;

and now it will work for any width of cnt[],
whereas 8'b1 might give the warning again if
you later change the code so that the register
is narrower than 8 bits.
--
Jonathan Bromley

 

[gabor]

On May 5, 7:12 pm, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:

Recent version of Xilinx sythesis xst tool flag e.g. following code sample

reg [7:0] cnt;
always @(posedge clk)
   cnt <= cnt +1,

with
WARNING:HDLCompiler:413 - "xxx" Line yyy: Result of 9-bit expression is
truncated to fit in 8-bit target.

You can silence the warning like

reg [7:0] cnt;
wire [8:0] adder = cnt + 1;
always @(posedge clk)
   cnt <= adder[7:0];

Does the warning make sense? Does the effort to silence the warning make
sense? Any better way?

Thanks

--
Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I haven't seen this myself (ISE 11.5). I wonder if it's smart
enough to figure whether the count can wrap?

i.e. does this give the same error:

reg [7:0] cnt;
always @(posedge clk)
cnt <= (cnt == 8'hff) ? 0 : cnt + 1;