Coding question

[Gregor]

Hello

I have got 2 reset signals. One reset is a global reset, which is active
when my whole Core is started or restarted.
Then I have got for a module a second rst which resets me the accumulator
after each computation. At the moment it looks
like this.

sync: process(clk, rst, rst_accu)
begin
if rst = '1' then
op1 <= (others => '0');
accu1 <= (others => '0');
elsif rst_accu = '1' then
op1 <= (others => '0');
accu1 <= (others => '0');
elsif clk'event and clk = '1' then
..........

Is it possible to write this in one if? Like in C where I can use "or" to
find out if one of the 2 cases is true?
somthing like this

If (rst ='1' | rst_accu='1') then

cheers
Greg

 

[Duane Clark]

Gregor wrote:

Hello

I have got 2 reset signals. One reset is a global reset, which is active
when my whole Core is started or restarted.
Then I have got for a module a second rst which resets me the accumulator
after each computation. At the moment it looks
like this.

sync: process(clk, rst, rst_accu)
begin
if rst = '1' then
op1 <= (others => '0');
accu1 <= (others => '0');
elsif rst_accu = '1' then
op1 <= (others => '0');
accu1 <= (others => '0');
elsif clk'event and clk = '1' then
.........

Is it possible to write this in one if? Like in C where I can use "or" to
find out if one of the 2 cases is true?
somthing like this

If (rst ='1' | rst_accu='1') then

Certainly that is possible, but you should reconsider it. You want to
make rst_accu a synchronous reset. Really, you do

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My real email is akamail.com@dclark (or something like that).

 

[Charles Bailey]

Sure, just code it as
If (rst='1' or rst_accu='1') then

but, as Duane pointed out, are these supposed to be synchronous or
asynchronous resets?

Charles Bailey

 

[Gregor]

Thanks for your answers, I wanna have asynchronous resets. So when I do it
this way it should be fine, shouldnt it?

sync: process(clk, rst, rst_accu)
begin
If (rst='1' or rst_accu='1') then
op1 <= (others => '0');
accu1 <= (others => '0');
elsif clk'event and clk = '1' then
..........


cheers
Gregor

"Charles Bailey" <ceb_misc@ultrasw.com> schrieb im Newsbeitrag
news:110tsn3dgf5pf08@corp.supernews.com...

Sure, just code it as
If (rst='1' or rst_accu='1') then

but, as Duane pointed out, are these supposed to be synchronous or
asynchronous resets?

Charles Bailey

 

[Hal Murray]

Thanks for your answers, I wanna have asynchronous resets. So when I do it
this way it should be fine, shouldnt it?

Why do you want asynchronous resets? Do you want your designs
to work reliabily?

This tangle gets discussed frequently in the FPGA group. Most
FPGA hardware has a global reset signal, but it's slow and hence
hard to use reliably. Consensus seems to be to use the global
signal to reset things and then to make a local synchronous
reset to control small chunks of logic.

Without the local synchronous reset, you have two problems.
The first is that the trailing edge of reset is asynchronous
so it will get to different parts of your circuit at different
times. If you are unlucky, they will straddle a clock so
some of your logic will see reset go away on one clock and
other parts will see it go away on the next clock.

It's possible (maybe even easy) to work around that. For example,
if the idle state of your FSM is the same as the reset and there
are no change-state requests active during reset then your FSM
won't be trying to change state so it won't get any errors.

Similar for a counter that has only 1 bit changing on the first
clock after reset. That's as long as the count doesn't have
to match actions in another part of the logic that also starts
working when reset goes away.

But do you want to analyze each chunk of logic carefully to make
sure it will work? Will you remember when you change something?

The next problem is metastability. Even if you only have one FF
changing on the first clock after reset ends, you still have to
consider what happens if that FF goes metastable. It's much simpler
to put the anti-metastable logic off to the side in a local
reset circuit. (Classic pair of FFs.)


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