CODING PROBLEMS

[Vhdl Learner]

I am trying to implement a divider using FSM+D modeling in VHDL. I
have used the bit_vector data type for my variables and port. It helps
me in shifting etc. But I am unable to do a bitwise substract
operation. Can anyone help me about how to do this. Thanks a lot in
advance.

waiting

 

[Paul Uiterlinden]

Vhdl Learner wrote:

I am trying to implement a divider using FSM+D modeling in VHDL. I
have used the bit_vector data type for my variables and port. It helps
me in shifting etc. But I am unable to do a bitwise substract
operation. Can anyone help me about how to do this. Thanks a lot in
advance.

http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#arithmetic

waiting

???
Waiting is not very instructive.

Paul.

 

[Kumaran Selvaratnam]

Correct me if I am wrong.

Your objective is to get bitwise subtract or
the following truth table properties??

x|y|output
0|0|0
0|1|1
1|0|1
1|1|0

This means this is effectively a bitwise xor.

check 'xor' function.

Good luck
Kumaran


Paul Uiterlinden wrote:

Vhdl Learner wrote:

I am trying to implement a divider using FSM+D modeling in VHDL. I
have used the bit_vector data type for my variables and port. It helps
me in shifting etc. But I am unable to do a bitwise substract
operation. Can anyone help me about how to do this. Thanks a lot in
advance.


http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#arithmetic

waiting


???
Waiting is not very instructive.

Paul.