Coding problem (beginner question)

[smu]

I am new in the VHDL world. I have a question that a lot
of people among you will be able to answer? I use often
the following description but with different bus width.
But I am obliged to declare the whole, each time I change
the bus width. My question is: Does there exist a way to
code the entity with the bus width as a parameter ?

Thank in advance

smu

---------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fd14ce is
Port ( ce : in std_logic;
clk : in std_logic;
clr : in std_logic;
d : in std_logic_vector(13 downto 0);
q : out std_logic_vector(13 downto 0));
end fd14ce;

architecture fd14ce_a of fd14ce is
begin
process (clk, clr) begin
if ( clr = '1') then
q <= (others => '0');
elsif ( rising_edge( clk) and ce='1') then
q <= d;
end if;
end process;
end fd14ce_a;

 

[Jamie]

Look up the keyword GENERIC

Jamie


"smu" <pas@d.adresse> wrote in message
news:3f2a2dde$0$1925$626a54ce@news.free.fr...

I am new in the VHDL world. I have a question that a lot
of people among you will be able to answer? I use often
the following description but with different bus width.
But I am obliged to declare the whole, each time I change
the bus width. My question is: Does there exist a way to
code the entity with the bus width as a parameter ?

Thank in advance

smu

---------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fd14ce is
Port ( ce : in std_logic;
clk : in std_logic;
clr : in std_logic;
d : in std_logic_vector(13 downto 0);
q : out std_logic_vector(13 downto 0));
end fd14ce;

architecture fd14ce_a of fd14ce is
begin
process (clk, clr) begin
if ( clr = '1') then
q <= (others => '0');
elsif ( rising_edge( clk) and ce='1') then
q <= d;
end if;
end process;
end fd14ce_a;

 

[Jonathan Bromley]

"smu" <pas@d.adresse> wrote in message
news:3f2a2dde$0$1925$626a54ce@news.free.fr...

I am new in the VHDL world. I have a question that a lot
of people among you will be able to answer? I use often
the following description but with different bus width.
But I am obliged to declare the whole, each time I change
the bus width. My question is: Does there exist a way to
code the entity with the bus width as a parameter ?

Yes, there are at least two possible methods.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Already there are two problems here:

1) You don't need any arithmetic packages for the "fd14ce"
design. I suggest it's better to USE only the packages
you really need.

2) It is a VERY BAD IDEA to use both std_logic_arith and
std_logic_unsigned. I guess you are using some FPGA
tools that add these lines automatically. It's very
bad style. Learn how to use the numeric_std package
for all your

entity fd14ce is
[14-bit edge-triggered register with asynchronous clear

and synchronous clock-enable]

Here are the two possible methods.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) Using a generic to set the width

library ieee;
use ieee.std_logic_1164.all;

entity fdce_N is
generic ( N: positive := 1 ); -- bus width
port ( ce : in std_logic;
clk : in std_logic;
clr : in std_logic;
d : in std_logic_vector(N-1 downto 0);
q : out std_logic_vector(N-1 downto 0)
);
end;

Your architecture can remain the same. When you create an
instance of a component that matches this entity, you need
a generic map in addition to a port map:

signal Source, Result: std_logic_vector(15 downto 0);
...
...
inst: fdce_N
generic map (N => 12)
port map (...
d => Source,
q => Result);

Or perhaps even better...

inst: fdce_N
generic map ( N => Source'length )
port map ...
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(2) Using unconstrained ports
library ieee;
use ieee.std_logic_1164.all;

entity fdce_any_width is
port ( ce : in std_logic;
clk : in std_logic;
clr : in std_logic;
d : in std_logic_vector;
q : out std_logic_vector
);
end;

The ports on this entity will automatically resize
to match the signal you connect to them. Once again
the architecture can remain the same.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When you use unconstrained ports, there is a risk that
some fool will connect different-size buses to the D
and Q ports. To protect against this it is a good idea
to put an assertion into the architecture:

architecture ...
... -- signal declarations
begin
assert D'LENGTH = Q'LENGTH
report "Input and output ports have different width"
severity FAILURE;

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Some synthesis tools don't handle unconstrained ports,
so try a simple example first, before you commit
to a lot of work. And of course you cannot synthesise
a design whose top level has unconstrained ports.

Good luck.
--
Jonathan Bromley, Consultant

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