Code problem

[Brandon Boyce]

I'm really really new to programming in VHDL. The program I have here
compiles with quite a few warnings but no errors. It doesn't do what I
want it to do. This program is for a school project. It creates a
signal going out to a digital to analog converter, through an op amp
to an oscilliscope. It's supposed to make a square wave, a sawtooth
wave, and a triangle wave. I simulated the code on the waveform editor
in Alter Max+PlusII. only get the results I want for the manual switch
of D0 - D7. Any help would be much appreciated

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;

ENTITY funcgen IS
PORT(
clk : IN STD_LOGIC;
sw1, sw2 : in std_logic;
D : IN std_logic_vector (7 downto 0);
Q : OUT STD_LOGIC_vector (7 downto 0)
);
END funcgen;

ARCHITECTURE a of funcgen IS
signal count : std_logic_vector ( 8 downto 0 ) := "00000000";
BEGIN
PROCESS (clk)

BEGIN
if ( sw1 = '0' and sw2 = '0') then -- manual pass
count <= D (7 downto 0);
end if;
IF (clk = '0' and sw1 = '0' and sw2 = '1') THEN -- square wave
count <= "000000000";
elsif (clk = '1' and sw1 = '0' and sw2 = '1' and count =
"000000000" ) then -- square wave
count <= "000000000";
end if;
iF (clk = '1' and sw1 = '1' and sw2 = '0') THEN -- sawtooth
wave
count <= count + "000000001";

elsif (clk = '1' and sw1 = '1' and sw2 = '0' and count =
"111111111") then -- sawtooth
count <= "000000000";
count <= count + "000000001";
end if;
if (clk = '1' and sw1 = '1' and sw2 = '0') then
count <= count + "000000001";

elsif (clk = '1' and sw1 = '1' and sw2 = '0' and count =
"111111111") then
count <= count - "000000001";


end if;

Q <= count (7 downto 0);
END PROCESS;
END a;

 

[Mike Treseler]

Brandon Boyce wrote:

I'm really really new to programming in VHDL. The program I have here
compiles with quite a few warnings but no errors. It doesn't do what I
want it to do.

Consider rewriting you code using the synchronous template:

process(reset,clock) is
-- declare local variables, functions, procedures here
begin
if (reset='1') then
-- asynch reset assignments
elsif rising_edge(clock) then
-- sequential statement ( <=, :=, if, case, for etc.)
-- sequential statement ( <=, :=, if, case, for etc.)
-- sequential statement ( <=, :=, if, case, for etc.)
-- sequential statement ( <=, :=, if, case, for etc.)

-- must make assignments ( <= ) to at least one
-- entity port (directly or indirectly)
-- to avoid a null synthesis.
end if;
end process;


Consider simulation before synthesis.

-- Mike Treseler