Code not being simulated by Modelsim

K

kb33

Guest
Hi,

I have the following piece of code which is probably too complicated
for the simulation tool. It just hangs:


`define INDEX_SZ 3
`define NUM_ELEMENTS 8

reg [`INDEX_SZ-1:0] var_b_comb,
var_c_comb;

reg [`INDEX_SZ*`NUM_ELEMENTS/2 - 1:0] var_c_vector_comb,

var_bxorc_vector_comb;


for (var_c_comb = 0; var_c_comb < `NUM_ELEMENTS; var_c_comb
= var_c_comb +1)
if ((var_c_comb ^ var_b_comb) > 1)
begin
var_c_vector_comb <= ((var_c_vector_comb <<
`INDEX_SZ) | var_c_comb);
var_bxorc_vector_comb <= ((var_bxorc_vector_comb <<
`INDEX_SZ) | (var_c_comb ^ var_b_comb));
end

//End of code..

What I would like to do is update the var_c_vector_comb and the
var_bxorc_vector_comb whenever the IF condition is satisfied. At the
same time, I need to preserve the previously stored values hence the
left shift operation. Also, the reason I have chosen NUM_ELEMENTS/2 in
the size of the two vectors is because I expect the IF condition to be
true for only half the number of elements. Any suggestions would be
appreciated.

Thanks
Kanchan
 
On 3 May 2007 09:50:23 -0700, kb33 <kanchan.devarakonda@gmail.com>
wrote:

Hi,

I have the following piece of code which is probably too complicated
for the simulation tool. It just hangs:
Click to expand...
Where is the code? Plainly it's procedural, so maybe it's inside
a zero-delay always block, hence the hang?

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Yes, this is a combinational always block with zero delay. If that is
the problem, then what would be another way to fill up the vector
without consuming too many clock cycles? If I break up the code into
pieces and perform the task in multiple clock cycles, then too many
clock cycles would be consumed just to fill up the vector as the value
of NUM_ELEMENTS increases.

Kanchan

On May 3, 1:26 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On 3 May 2007 09:50:23 -0700, kb33 <kanchan.devarako...@gmail.com
wrote:

Hi,

I have the following piece of code which is probably too complicated
for the simulation tool. It just hangs:

Where is the code? Plainly it's procedural, so maybe it's inside
a zero-delay always block, hence the hang?

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
kb33 wrote:
`define INDEX_SZ 3
`define NUM_ELEMENTS 8

reg [`INDEX_SZ-1:0] var_b_comb,
var_c_comb;

for (var_c_comb = 0; var_c_comb < `NUM_ELEMENTS; var_c_comb
= var_c_comb +1)
Click to expand...
Since var_c_comb is only 3 bits wide, the biggest value it can store
is 7.
When you increment it from 7, it wraps around to 0. Since it will
always be
less than 8, your loop condition is always true, and the loop will
never
exit. You have written an infinite loop.
 
On 3 May 2007 11:21:00 -0700, sharp@cadence.com wrote:

Since var_c_comb is only 3 bits wide, the biggest value it can store
is 7.
When you increment it from 7, it wraps around to 0. Since it will
always be
less than 8, your loop condition is always true, and the loop will
never
exit. You have written an infinite loop.
Click to expand...
oops, I missed that standard Gotcha!

Good catch.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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