code is not synthesizing

[rkchaitanya87]

Hi, i have written the 4bit booth multiplier code in verilog where for different 2bit combinations of multiplier i am following booth algorithm to perform the operation. but when i am synthesizing it, it is not completing and i think it goes infinitely. Please help me for the code.

module multi(
input [3:0] mp,
input [3:0] mc,
output [7:0] result,
input start,
input clk);
reg [7:0] br,nbr;
reg [7:0] acqr;
reg qn1,temp;
reg i;
always@(posedge clk)
begin
if(start)
begin
acqr[7:4] = 4'b0000;
acqr[3:0] = mp;
br[7:4] = mc;
br[3:0] = 4'b0000;
nbr[7:4] = ~mc + 1'b1;
nbr[3:0] = 4'b0000;
qn1 = 1'b0;
end
else
begin
for(i=0;i<=3;i=i+1)
begin
if(acqr[0]==1'b0 && qn1==1'b0)
begin
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
else if(acqr[0]==1'b0 && qn1== 1'b1)
begin
acqr[7:0] = acqr[7:0]+br[7:0];
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
else if(acqr[0]==1'b1 && qn1== 1'b0)
begin
acqr[7:0] = acqr[7:0]+nbr[7:0];
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
else if(acqr[0]==1'b0 && qn1== 1'b1)
begin
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
end
end
end
endmodule

 

[GaborSzakacs]

rkchaitanya87 wrote:

Hi, i have written the 4bit booth multiplier code in verilog where for different 2bit combinations of multiplier i am following booth algorithm to perform the operation. but when i am synthesizing it, it is not completing and i think it goes infinitely. Please help me for the code.

module multi(
input [3:0] mp,
input [3:0] mc,
output [7:0] result,
input start,
input clk);
reg [7:0] br,nbr;
reg [7:0] acqr;
reg qn1,temp;
reg i;
always@(posedge clk)
begin
if(start)
begin
acqr[7:4] = 4'b0000;
acqr[3:0] = mp;
br[7:4] = mc;
br[3:0] = 4'b0000;
nbr[7:4] = ~mc + 1'b1;
nbr[3:0] = 4'b0000;
qn1 = 1'b0;
end
else
begin
for(i=0;i<=3;i=i+1)
begin
if(acqr[0]==1'b0 && qn1==1'b0)
begin
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
else if(acqr[0]==1'b0 && qn1== 1'b1)
begin
acqr[7:0] = acqr[7:0]+br[7:0];
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
else if(acqr[0]==1'b1 && qn1== 1'b0)
begin
acqr[7:0] = acqr[7:0]+nbr[7:0];
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
else if(acqr[0]==1'b0 && qn1== 1'b1)
begin
temp =qn1;
qn1 = acqr[0];
acqr[6:0] = acqr[7:1];
acqr[7]=temp;
end
end
end
end
endmodule

You must have a pretty brain-dead synthesis tool. XST (Xilinx) came up
with this error message:

ERROR:HDLCompiler:569 - "<path>\multi.v" Line 27: Loop count limit
exceeded. Condition is never false.

Clearly this is caused by your variable "i" which is too small to
hold the value 3. I normally declare loop variables to be
integers. You don't necessarily need the 32 bits, but it doesn't
hurt and doesn't add hardware because they don't represent logic
that gets synthesized.

So just change:

reg i;

to:

integer i;

--
Gabor