S
srinukasam
Guest
hello
iam writing a code for comparing the array with input vector parallely.
could you please see once . is this code will work ( i mean it work for my
above mentioned requirement or not). and the function iam using in my code
is described in package.
ENTITY nest_addr IS
generic(pstate_width:integer :=8;
mem_width:integer:=128; --out from mem..in to logic
no_of_ns: integer:=16; --for array size .this block
index: integer :=4);
port( clk :in std_logic;
diff_states: in std_logic_vector(mem_width-1 downto 0 );
pstate: in std_logic_vector(pstate_width-1 downto 0);
data
ut std_logic_vector(index-1 downto 0));
--
ARCHITECTURE nest_addr_beh OF nest_addr IS
type temp is array ( o to no_of_ns-1) of std_logic_vector(0 to
pstate_width-1);
signal temp_c:temp;
signal temp_vect :std_logic_vector (no_of_ns-1 downto 0);
signal data_temp:integer:=0;
begin
assignrocess(clk)
variable first:integer:=1;
variable second:integer:=0;
begin
for i in 0 to no_of_ns loop
if i =0 then
temp_c(i)<=diff_states(0 to pstate_width-1);
else
first:=first+pstate_width;
second:=first+(pstate_width-1);
temp_c(i)<= diff_states(first to second);
end if;
end loop;
end process assign;
ns:for i in 0 to no_of_ns-1 generate
if temp_c(i)= pstate then --here its showing error
data_temp<=i;
end if;
end generate ns;
conv: process(data_temp)
begin
data<=int_to_vect(4,data_temp);
end process;
end ARCHITECTURE nest_addr_beh;
thank you
iam writing a code for comparing the array with input vector parallely.
could you please see once . is this code will work ( i mean it work for my
above mentioned requirement or not). and the function iam using in my code
is described in package.
ENTITY nest_addr IS
generic(pstate_width:integer :=8;
mem_width:integer:=128; --out from mem..in to logic
no_of_ns: integer:=16; --for array size .this block
index: integer :=4);
port( clk :in std_logic;
diff_states: in std_logic_vector(mem_width-1 downto 0 );
pstate: in std_logic_vector(pstate_width-1 downto 0);
data
ut std_logic_vector(index-1 downto 0));--
ARCHITECTURE nest_addr_beh OF nest_addr IS
type temp is array ( o to no_of_ns-1) of std_logic_vector(0 to
pstate_width-1);
signal temp_c:temp;
signal temp_vect :std_logic_vector (no_of_ns-1 downto 0);
signal data_temp:integer:=0;
begin
assign
rocess(clk)variable first:integer:=1;
variable second:integer:=0;
begin
for i in 0 to no_of_ns loop
if i =0 then
temp_c(i)<=diff_states(0 to pstate_width-1);
else
first:=first+pstate_width;
second:=first+(pstate_width-1);
temp_c(i)<= diff_states(first to second);
end if;
end loop;
end process assign;
ns:for i in 0 to no_of_ns-1 generate
if temp_c(i)= pstate then --here its showing error
data_temp<=i;
end if;
end generate ns;
conv: process(data_temp)
begin
data<=int_to_vect(4,data_temp);
end process;
end ARCHITECTURE nest_addr_beh;
thank you