CMOS 4000 series Logic levels - Related to VDD

[Klaus Vestergaard Kragelu]

Hi there

Does anyone know why the logic levels of the CD4000 series, specifically the
CD4007 input logic levels (www.microdesign.dk/tmp/cd4007_datasheet.pdf)
change with the supply voltage?

Thanks

Klaus

 

[Jim Thompson]

On Fri, 12 Nov 2004 21:53:47 +0100, "Klaus Vestergaard Kragelund"
<klauskvik@hotmail.com> wrote:

Hi there

Does anyone know why the logic levels of the CD4000 series, specifically the
CD4007 input logic levels (www.microdesign.dk/tmp/cd4007_datasheet.pdf)
change with the supply voltage?

Thanks

Klaus

Yes ;-)

See below.....




























The threshold of CMOS logic is determined by the relative "strengths"
of the opposing P- and N-channel devices.

"Strength" of a device is determined by its "area" (W/L) and its
type... N-type devices for a given area are generally 3-4 times
"stronger than P-type devices.

_CMOS_threshold_ logic parts (CD..., ..HC..., etc.) are generally
designed so that threshold is at the mid-point of the supply. But
specifications will say 30% to 70% of supply to account for processing
variations, and to allow the sale of crap ;-)

CMOS parts designed to interface to TTL will have a nominal threshold
sized to 1.4V at the design power supply, but will vary
percentage-wise with supply just as standard CMOS parts do.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Joerg]

Hi Klaus,

Jim explained it all, nothing to add from my side. One remark regarding
the 4007. These are generally non-buffered devices and there is a U or
UB behind the number. Level variation on these will be more pronounced
since the inverter in this chip consists of just one pair and not three,
meaning the gain is much lower and the threshold is much shallower than,
for example, in an inverter of the CD4049BE. There is also an unbuffered
version of the 4049.

Regards, Joerg

http://www.analogconsultants.com

 

[Kevin Aylward]

Joerg wrote:

Hi Klaus,

Jim explained it all, nothing to add from my side. One remark
regarding the 4007. These are generally non-buffered devices and
there is a U or UB behind the number.

This phrasing is a bit misleading. The 4007 is a set of discrete
transistors. The concept of buffered and unbufferd doesn't apply to
individual transistors. You can connect up the 4007 as either a buffered
or unbufferd inverter, but you can also use the transistors in any non
digital way you like.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Guy Macon]

Phillips HC user guide:
http://www.standardproducts.philips.com/support/techdocs/logic/pdf/hcguide.pdf

Fairchild HC app note:
http://www.fairchildsemi.com/an/AN/AN-319.pdf

 

[Genome]

"Guy Macon" <http://www.guymacon.com> wrote in message
news:10pd6f669o28q2d@corp.supernews.com...

Phillips HC user guide:

http://www.standardproducts.philips.com/support/techdocs/logic/pdf/hcguide.p

df

Fairchild HC app note:
http://www.fairchildsemi.com/an/AN/AN-319.pdf

Space
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