"Close" Timing and STA

[Anand P. Paralkar]

Hi,

I would like to know:

a. What is meant by "Close" Timing for an *ASIC*, and,
b. What are the typical tasks that an STA engineer does?
(I know a. above, could be an answer, but I am looking
for a little more detailed answer. )

(Request you to support your explaination with examples if
possible.)

Thanks,
Anand

PS: Any idea if comp.cad.synthesis is active?

 

Timing closure is to fix setup/hold time violation. Set correct
constrain and find all violations in STA. Then the hard part is Timing
ECO.
Here is one example to use netlist processing tool GOF to do timing
ECO.
http://www.nandigits.com/timing_eco.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

 

[Kunal Shenoy]

Hi Anand,
Timing as related to FPGAs which is similar to ASICs:
Most digital designs are based on RTL (Register Transfer Logic) which
consists of combination logic placed in between pairs of registers.
source flop -> combinational logic -> destination flop.
In one clock cycle, the source flop has to output its data (clk to
output delay), the data has to pass through the combinational logic
(propagation delay) and the destination flop has to have enought time
to register it before the next active clock edge (setup requirement).
Thus the following equation should be met, clock_period > clk_to_out +
propagation_delay + setup_time. If this is not met, then the data might
not be registered by the destination flop and your system fails. There
are some additions to the equation such as jitter which you would need
to take into consideration.
There are also pad-to-pad, input pin and output-pin constraints that
need to be looked at but they are all based on the same basic
principle.
The Xilinx website is a good (great ) source for digital design
concepts. ftp://ftp.xilinx.com/pub/documentation/misc/timingcsts6i.pdf
You could also look for more information in synthesis manuals such as
that available by Synopsys, Mentor Graphics etc.

Kunal
Xilinx