Clocking data in verilog

[Paul Chapman]

I'm new to Verilog, but I'm trying a simple Verilog project that stores data
from an incoming data bus on rising edge. A full description is below:



Textual Description:



I have a four bit wide data bus; it's going to read in three consecutive
4-bit values. On the rising edge it reads the first value, my Verilog code
stores this as rData_0, on the next rising edge it reads the data and stores
this as rData_1, the next rising edge it reads in the data and stores this
as rData_2, on the next rising edge the data is read and stored in rData_0
and the program continues to loop through until an async reset is applied.



Any help would be greatly appreciated.



Regards,



Paul.

 

[Andy Peters]

Paul Chapman wrote:

I'm new to Verilog, but I'm trying a simple Verilog project that stores data
from an incoming data bus on rising edge. A full description is below:

Textual Description:

I have a four bit wide data bus; it's going to read in three consecutive
4-bit values. On the rising edge it reads the first value, my Verilog code
stores this as rData_0, on the next rising edge it reads the data and stores
this as rData_1, the next rising edge it reads in the data and stores this
as rData_2, on the next rising edge the data is read and stored in rData_0
and the program continues to loop through until an async reset is applied.

Consider using a state machine. On every clock tick, you store
incoming data into rData_0, 1 or 2 depending on which state you're in,
and then you bump to the next state.

-a