clock_signal constraint

[rekz]

I have a behaviour module which takes the clock from my spartan board
and then outputs a clock with a lower rate. However I got the
following warning when synthesizing:

(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not
automatically buffered by XST with BUFG/BUFR resources. Please use the
buffer_type constraint in order to insert these buffers to the clock
signals to help prevent skew problems.

I checked the manual and it says to do the following:

// synthesis attribute clock_signal [of] signal_name [is] “yes”;

I am not sure where to put this line of code at. My clock from the LCD
is labelled as Clk and the output from the behavior module is ClkOut,
so then should I do:

// synthesis attribute clock_signal ClkOut is “yes”;

 

[David Rogoff]

This is not a Verilog question. It is an FPGA implementation question.
Please post to comp.arch.fpga, not comp.lang.verilog

On 2010-05-01 10:14:23 -0700, rekz said: