clock

[chuk]

When configuring a virtex fpga with a prom in master serial mode, how
is the clock generated by the fpga. I presume I don’t need to
input any other clock other than my normal fast clock of 100MHz.

 

[Peter Alfke]

In master mode the configuration clock is generated by an FPGE-internal
RC oscillator. The frequency is not very accurate or stable, but good
enough for the purpose.

Peter Alfke
===============
chuk wrote:

When configuring a virtex fpga with a prom in master serial mode, how
is the clock generated by the fpga. I presume I don’t need to
input any other clock other than my normal fast clock of 100MHz.