clock synthesis with RocketIO

[Robert Sefton]

I'm looking at using a V2P RocketIO transmitter to synthesize a clock by
bypassing the 8B10B encoder and feeding it 01010101 data words. I would
vary the output clock frequency by varying the reference clock and/or
the data pattern (00110011, 00001111, etc.). Is there any reason this
would not work?

Thanks,

Robert

(Reply email address is bogus. Please reply to group.)

 

[Peter Alfke]

I see no reason to doubt this. In fact, I intend to do the same thing.
Note that in V2Pro the parallel interface is 10 or 20 bits wide, not 8 or 16
bits. This requires some digital trickery once you go beyond 4-bit patterns
on the parallel side. Let me know if you run into any snags...
Peter Alfke

From: "Robert Sefton" <rsefton@abc.net
Newsgroups: comp.arch.fpga
Date: Tue, 3 Aug 2004 13:36:09 -0700
Subject: clock synthesis with RocketIO

I'm looking at using a V2P RocketIO transmitter to synthesize a clock by
bypassing the 8B10B encoder and feeding it 01010101 data words. I would
vary the output clock frequency by varying the reference clock and/or
the data pattern (00110011, 00001111, etc.). Is there any reason this
would not work?

Thanks,

Robert

(Reply email address is bogus. Please reply to group.)

 

[Josh Model]

I was actually thinking about implemeting something similar, but for direct
RF modulation. Plan was to have m-phases of a clock as the data pattern,
update it at the modulation rate and bandpass filter the output. Haven't
tried it out yet, but I imagine you end up with M-PSK around the carrier.
Unfortunately Your maximum RF frequency drops precipitously as m-increases.
Yeah, it's probably easier to use an LO and a mixer, but getting BPSK
through S -band would be pretty nifty coming from an FPGA. Anyone tried
this or any comments on feasibility?

--Josh

Anyone know if you could you could
"Peter Alfke" <peter@xilinx.com> wrote in message
news:BD354D8A.7D3A%peter@xilinx.com...

I see no reason to doubt this. In fact, I intend to do the same thing.
Note that in V2Pro the parallel interface is 10 or 20 bits wide, not 8 or
16
bits. This requires some digital trickery once you go beyond 4-bit
patterns
on the parallel side. Let me know if you run into any snags...
Peter Alfke


From: "Robert Sefton" <rsefton@abc.net
Newsgroups: comp.arch.fpga
Date: Tue, 3 Aug 2004 13:36:09 -0700
Subject: clock synthesis with RocketIO

I'm looking at using a V2P RocketIO transmitter to synthesize a clock by
bypassing the 8B10B encoder and feeding it 01010101 data words. I would
vary the output clock frequency by varying the reference clock and/or
the data pattern (00110011, 00001111, etc.). Is there any reason this
would not work?

Thanks,

Robert

(Reply email address is bogus. Please reply to group.)