N
niks
Guest
Hi Everyone,
Can some one tell me whats useful skew?
Can some one tell me whats useful skew?
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Guest
On Wed, 3 Dec 2008 10:15:20 -0800 (PST), niks <gtalk.nikhil@gmail.com>
wrote:
arrival of clock to all the flops are the same so there is zero skew
between the clocks; at least that is the goal in designing a clock
tree. Useful skew is the methodoly of creating a clock tree which has
non-zero skew by design when it is "useful". Skew is useful when the
combinational delays between registers are not balanced in a design
and this unbalance can be taken advantage of by moving the clock delay
of the target of the long path.
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
wrote:
Most digital circuits are designed with zero skew constraint ie theHi Everyone,
Can some one tell me whats useful skew?
arrival of clock to all the flops are the same so there is zero skew
between the clocks; at least that is the goal in designing a clock
tree. Useful skew is the methodoly of creating a clock tree which has
non-zero skew by design when it is "useful". Skew is useful when the
combinational delays between registers are not balanced in a design
and this unbalance can be taken advantage of by moving the clock delay
of the target of the long path.
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
N
niks
Guest
On Dec 4, 12:07 am, k...@dspia.com wrote:
So in this way we are avoiding setup violation right!!On Wed, 3 Dec 2008 10:15:20 -0800 (PST), niks <gtalk.nik...@gmail.com
wrote:
Hi Everyone,
Can some one tell me whats useful skew?
Most digital circuits are designed with zero skew constraint ie the
arrival of clock to all the flops are the same so there is zero skew
between the clocks; at least that is the goal in designing a clock
tree. Useful skew is the methodoly of creating a clock tree which has
non-zero skew by design when it is "useful". Skew is useful when the
combinational delays between registers are not balanced in a design
and this unbalance can be taken advantage of by moving the clock delay
of the target of the long path.
DSPIA INC.
ASIC/FPGA Design Serviceshttp://www.dspia.com
Guest
On Sat, 6 Dec 2008 14:31:48 -0800 (PST), niks <gtalk.nikhil@gmail.com>
wrote:
designs can't.
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
wrote:
Yes, useful skew enables you meet timing in cases where zero-skewOn Dec 4, 12:07 am, k...@dspia.com wrote:
On Wed, 3 Dec 2008 10:15:20 -0800 (PST), niks <gtalk.nik...@gmail.com
wrote:
Hi Everyone,
Can some one tell me whats useful skew?
Most digital circuits are designed with zero skew constraint ie the
arrival of clock to all the flops are the same so there is zero skew
between the clocks; at least that is the goal in designing a clock
tree. Useful skew is the methodoly of creating a clock tree which has
non-zero skew by design when it is "useful". Skew is useful when the
combinational delays between registers are not balanced in a design
and this unbalance can be taken advantage of by moving the clock delay
of the target of the long path.
DSPIA INC.
ASIC/FPGA Design Serviceshttp://www.dspia.com
So in this way we are avoiding setup violation right!!
designs can't.
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
V
vlsichipdesigner@gmail.co
Guest
On Dec 7, 6:32 am, k...@dspia.com wrote:
To have a better understanding visit this link
http://www.vlsichipdesign.com/clock_tree6.jpg
Here you are delaying the capture clock or skewing the capture clock
my prayers
hi,On Sat, 6 Dec 2008 14:31:48 -0800 (PST), niks <gtalk.nik...@gmail.com
wrote:
On Dec 4, 12:07 am, k...@dspia.com wrote:
On Wed, 3 Dec 2008 10:15:20 -0800 (PST), niks <gtalk.nik...@gmail.com
wrote:
Hi Everyone,
Can some one tell me whats useful skew?
Most digital circuits are designed with zero skew constraint ie the
arrival of clock to all the flops are the same so there is zero skew
between the clocks; at least that is the goal in designing a clock
tree. Useful skew is the methodoly of creating a clock tree which has
non-zero skew by design when it is "useful". Skew is useful when the
combinational delays between registers are not balanced in a design
and this unbalance can be taken advantage of by moving the clock delay
of the target of the long path.
DSPIA INC.
ASIC/FPGA Design Serviceshttp://www.dspia.com
So in this way we are avoiding setup violation right!!
Yes, useful skew enables you meet timing in cases where zero-skew
designs can't.
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Serviceshttp://www.dspia.com- Hide quoted text -
- Show quoted text -
To have a better understanding visit this link
http://www.vlsichipdesign.com/clock_tree6.jpg
Here you are delaying the capture clock or skewing the capture clock
my prayers