Clock Signals

U

u_stadler@yahoo.de

Guest
Hi

I have antoher question: I generate a clock signal with logic. when i
synthesize i get the following message:

" (*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic. "

I'm using the ISE Webpack and a SParten 3. What do i have to do here?

Thanks
urban
 
I got similar messages. Without seeing your code I am not sure how
similar the circumstances are. In my case, I had some internally
generated strobes which are, of course, clock signals and a number of
external clocks (inputs). What the synthesis software wants you to do
is to specify the major clock signals so it can use clock buffers and
try to minimize clock delay problems. By the way, the term
CLOCK_SIGNAL, according to Xilinx's own help is obsolete, but will
still be accepted. Here is an example of how to designate the signals
so that they will be buffered by clock buffers (bufgce is the
designation for a clock buffer).

architecture arch_pulse_gen of pulse_generator is

attribute bufgce : string;
attribute bufgce of clk : signal is "yes";
attribute bufgce of slave_1_clk : signal is "yes";

The clock signals here are all inputs; I don't know if this is
appropriate for internally generated clocks. I hope this helps.

Charles
 
Clocks in a programmable logic devices are usually run on dedicated
channels or buffers. In order to determine which signals are placed on
these buffers, of which there is a limited quanity, the synthesizer
needs to know which signals are clocks and the timing paramaters
associated with these clocks. You are using a signal in your design as
a (combinatorial logic) clock, which may or may not be acceptible as
far as the implementation goes. I would recommend that your 'clock' be
driven by the output of a flip-flop. Preferably, your combinatorial
signal will activate a clock enable on the FF and the output will be
toggled by a 'hard' clock signal. Part of the problem with
combinatorial clocks is that they suffer from timing issues associated
with being created by logic that can have a variable timing and can
glitch. The implementation above will help reduce this probability.

Next, you will need to tell ISE that your signal is a clock and
specifiy the timing paramaters of this clock. There should be a menu
option for this purpose. Unfortunately, I am not familiar with ISE and
can't give you specifics here, but the help menu should be able to tell
you how to do it.
 
Hi

Thanks for the aswers. But I still didn't resolve the problem. Here is
the code and what I'm trying to do: I have an input clock of 50 MHZ
which i divide using a DCM so i get 24 MHZ. then i divide these 24MHZ
by 6 to get the 4MHZ i need for my SPI Interface. The reaso why i first
go to 24 and than to 4 MHZ is that the DCM's frequency synthesis can't
generate output frequencies below 18 MHZ.
When i do what Charles suggested i still get the warning. any help
would be appriciated.

Thanks
Urban


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity Top is
Port ( CLK : in std_logic;
RESET : in std_logic;
SPI_CLK : out std_logic;
SPI_IN : out std_logic;
SPI_OUT : in std_logic;
Test : out std_logic;
SPI_CS : out std_logic);
end Top;

architecture Behavioral of Top is


signal s_4MHZ_Count : integer range 0 to 7;
signal s_Next_4MHZ_Count : integer range 0 to 7;

signal CLK_4MHZ : std_logic;
signal CLK_24MHZ : std_logic;
signal Clock_RESET : std_logic;
signal s_RESET : std_logic;
signal s_CLock_Locked : std_logic;

COMPONENT Sensor_Interface
Port( CLK : in std_logic;
RESET : in std_logic;
SPI_CLK : out std_logic;
SPI_IN : out std_logic;
SPI_OUT : in std_logic := '0';
SPI_CS : out std_logic;
Data : out std_logic_vector(7 downto 0);
Data_Ready : out std_logic;
Data_Reset : out std_logic);
end COMPONENT;

COMPONENT Clock
Port( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end COMPONENT;

begin


I_Clock : Clock
port map( CLKIN_IN => CLK,
RST_IN => Clock_RESET,
CLKFX_OUT => CLK_24MHZ,
CLKIN_IBUFG_OUT => open,
LOCKED_OUT => s_Clock_Locked);


I_Sensor_Interface : Sensor_Interface
port map( CLK => CLK_4MHZ,
RESET => s_RESET,
SPI_CLK => SPI_CLK,
SPI_IN => SPI_IN,
SPI_OUT => SPI_OUT,
SPI_CS => SPI_CS,
Data => open,
Data_Ready => Test,
Data_Reset => open);



RST: process(RESET, s_Clock_Locked)
begin

Clock_RESET <= not RESET;

s_RESET <= '0';

if RESET = '1' and s_Clock_Locked = '1' then

s_RESET <= '1';
end if;

end process RST;

CLK_DV: process(s_4MHZ_Count)
begin

s_Next_4MHZ_Count <= s_4MHZ_Count + 1;

CLK_4MHZ <= '0';


if s_4MHZ_Count > 4 then

s_Next_4MHZ_Count <= 0;
end if;

if s_4MHZ_Count > 2 then

CLK_4MHZ <= '1';
end if;

end process CLK_DV;


CLK_DV_SYNC: process(RESET, CLK_24MHZ)
begin

if RESET = '0' then

s_4MHZ_Count <= 0;

elsif CLK_24MHZ'event and CLK_24MHZ = '1' then

s_4MHZ_Count <= s_Next_4MHZ_Count;

end if;


end process CLK_DV_SYNC;


end Behavioral;
 
From what I can tell, there is nothing wrong with your code. The
problem is in that you are generating 'signals' that are port mapped to
Click to expand...
the clk inputs of other blocks. ISE is detecting this, but does not
have enough information to determine how to handle them correctly.

In the tool I typically use, Quartus, there is an options under
settings that you can specify signals by name as being a clock, either
stand alone or derived, and specify the timing paramaters of the clock.
I do not know if ISE has a similar menu option. According to the post
from Charles, signals have a clk 'attribute' that can be set. From his
example, it looks as though these signals are also being routed on
global buffers (bufgce).

One possibility that comes to mind, and this is where I had difficulty,
is that the clock determination is being done by the synthesizer and
fitter programs. These programs assign a form of global node name to
the signals in a block, much like name mangling in C++. This way two
blocks can both have a name clk, but can be resolved to totally
different signals. It may be necessary to use these global names in
the assignment of clock attributes, especially if this is done through
a menu option, like in Quartus.

I am sorry if this isn't of much help to you, but as I indicated I am
not familiar enough with ISE to give you implementation specific
details.
 
Hi,

You are clearly wishing to generate a clock signal for use by numerous
flip flops.....there are only a few dedicated ("skewless") specialised
clock networks on the Xilinx FPGAs, the exact number depends on the
specific device (eg 8 on most S3 devices). There are specialist
buffers used to drive these networks and the logic within the slices can
select from these different clock distribution nets.

In answer to you question, for a "global" clock it is simplest to
directly instantiate the required buffer, if you dont need a clock
enable (eg as a power saving measure) the simplest is to include the
UNISIM library and instantiate the "BUFG" component (two port: I and O,
you should be able to figure out the rest).... For further info: in ISE
invoke the help lightbulb from the toolbar and look under VHDL > Device
Primitive Instantiation > FPGA > Clock Components > Clock Buffers ....

For more details on getting the most out of the DCMs have a look at the
Xilinx application note on using DCMs....

All the best,

Tim

u_stadler@yahoo.de wrote:

Hi

Thanks for the aswers. But I still didn't resolve the problem. Here is
the code and what I'm trying to do: I have an input clock of 50 MHZ
which i divide using a DCM so i get 24 MHZ. then i divide these 24MHZ
by 6 to get the 4MHZ i need for my SPI Interface. The reaso why i first
go to 24 and than to 4 MHZ is that the DCM's frequency synthesis can't
generate output frequencies below 18 MHZ.
When i do what Charles suggested i still get the warning. any help
would be appriciated.

Thanks
Urban


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity Top is
Port ( CLK : in std_logic;
RESET : in std_logic;
SPI_CLK : out std_logic;
SPI_IN : out std_logic;
SPI_OUT : in std_logic;
Test : out std_logic;
SPI_CS : out std_logic);
end Top;

architecture Behavioral of Top is


signal s_4MHZ_Count : integer range 0 to 7;
signal s_Next_4MHZ_Count : integer range 0 to 7;

signal CLK_4MHZ : std_logic;
signal CLK_24MHZ : std_logic;
signal Clock_RESET : std_logic;
signal s_RESET : std_logic;
signal s_CLock_Locked : std_logic;

COMPONENT Sensor_Interface
Port( CLK : in std_logic;
RESET : in std_logic;
SPI_CLK : out std_logic;
SPI_IN : out std_logic;
SPI_OUT : in std_logic := '0';
SPI_CS : out std_logic;
Data : out std_logic_vector(7 downto 0);
Data_Ready : out std_logic;
Data_Reset : out std_logic);
end COMPONENT;

COMPONENT Clock
Port( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end COMPONENT;

begin


I_Clock : Clock
port map( CLKIN_IN => CLK,
RST_IN => Clock_RESET,
CLKFX_OUT => CLK_24MHZ,
CLKIN_IBUFG_OUT => open,
LOCKED_OUT => s_Clock_Locked);


I_Sensor_Interface : Sensor_Interface
port map( CLK => CLK_4MHZ,
RESET => s_RESET,
SPI_CLK => SPI_CLK,
SPI_IN => SPI_IN,
SPI_OUT => SPI_OUT,
SPI_CS => SPI_CS,
Data => open,
Data_Ready => Test,
Data_Reset => open);



RST: process(RESET, s_Clock_Locked)
begin

Clock_RESET <= not RESET;

s_RESET <= '0';

if RESET = '1' and s_Clock_Locked = '1' then

s_RESET <= '1';
end if;

end process RST;

CLK_DV: process(s_4MHZ_Count)
begin

s_Next_4MHZ_Count <= s_4MHZ_Count + 1;

CLK_4MHZ <= '0';


if s_4MHZ_Count > 4 then

s_Next_4MHZ_Count <= 0;
end if;

if s_4MHZ_Count > 2 then

CLK_4MHZ <= '1';
end if;

end process CLK_DV;


CLK_DV_SYNC: process(RESET, CLK_24MHZ)
begin

if RESET = '0' then

s_4MHZ_Count <= 0;

elsif CLK_24MHZ'event and CLK_24MHZ = '1' then

s_4MHZ_Count <= s_Next_4MHZ_Count;

end if;


end process CLK_DV_SYNC;


end Behavioral;
Click to expand...
 
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