Clock signal in xilinx ISE?

[Tobias Weingartner]

I'm trying to put together a simple DCO style circuit, using a counter
to count a number of edges, and flipping a register each time my counter
reaches zero. For some reason xilinx ISE software does not find my clock
signal? Any way to "educate" it? (Newbie alert!)

Can someone give me a hand with what I'm (not?) doing here? Basically
the Xst is telling me various things, all of which are hard to believe.


module dco(clk,reset,enable,load,data,q);
input clk; // sysnthesis attribute clock_signal of clk is yes
input reset;
input enable;
input load;
input [13:0] data;
output reg q;

reg [13:0] count;
reg [13:0] stage;

// Handle reset, make quiet
always @(negedge reset) begin
if(~reset) begin
count <= 0;
stage <= 0;
//q <= 0; // Problematic, why?
end
end

// Stage && Load
always @(negedge load) begin
stage <= data;
if(~|count)
count <= data;
end

// Reload && Counter
// Why do I need both these blocks, why can't I just say
// on any transition of "clk"?
always @(posedge clk) begin
case (count)
0:
count <= stage;
1: begin
count <= stage;
q <= ~q;
end
default
count <= count - 1;
endcase
end
always @(negedge clk) begin
case (count)
0:
count <= stage;
1: begin
count <= stage;
q <= ~q;
end
default
count <= count - 1;
endcase
end

endmodule


Thank you for any help,

--
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[John_H]

For synthesis, your registers should be in one "always" block. Also, note
that few architectures allow both posedge clk and negedge clk triggering for
a single register; the silicon is designed for a single edge. For those
architectures that do support dual clocks, the synthesis package usually
offers implementation templates in the online help.

If you have an asynchronous reset, a load is usually synchronous with the
clock.

Something like:
always @(posedge clk or negedge nRst)
if( !nRst ) Count <= 0; // asynchronous
else if( !nLoad ) Count <= Data; // synchronous load - Data must be
synchronous to Clk
else if( Count==0 ) Count <= Data; // Reload
else Count <= Count -1;

If you want a faster clock (and the clock is continuous) consider the DCM to
increase the input frequency.


"Tobias Weingartner" <weingart@cs.ualberta.ca> wrote in message
news:slrnd0fvmm.hv.weingart@irricana.cs.ualberta.ca...

I'm trying to put together a simple DCO style circuit, using a counter
to count a number of edges, and flipping a register each time my counter
reaches zero. For some reason xilinx ISE software does not find my clock
signal? Any way to "educate" it? (Newbie alert!)

Can someone give me a hand with what I'm (not?) doing here? Basically
the Xst is telling me various things, all of which are hard to believe.

[snip]

 

[Tobias Weingartner]

In article <se6Od.8$iV.230@news-west.eli.net>, John_H wrote:

For synthesis, your registers should be in one "always" block. Also, note
that few architectures allow both posedge clk and negedge clk triggering for
a single register; the silicon is designed for a single edge. For those
architectures that do support dual clocks, the synthesis package usually
offers implementation templates in the online help.

Hmm... should the synthesis not be able to extrapolate into multiple
registers clocked on different edges, with the approriate logic added
to make it look "right"? I must be naiive... guess I go back and
try to figure it out explicitly.

If you have an asynchronous reset, a load is usually synchronous with the
clock.

Something like:
always @(posedge clk or negedge nRst)
if( !nRst ) Count <= 0; // asynchronous
else if( !nLoad ) Count <= Data; // synchronous load - Data must be
synchronous to Clk
else if( Count==0 ) Count <= Data; // Reload
else Count <= Count -1;

If you want a faster clock (and the clock is continuous) consider the DCM to
increase the input frequency.

Yikes, I'm not sure I understand 1/2 of this. Basically, I'm trying to
have a generic clock divider. Preferably something that will count edges,
not cycles. The behaviour I'm looking for are:

Async reset, reset all values to zero, inhibit any output.

Async load, load into a staging register, and upon expiry of the
current counter, we use the new value (to try and prevent "short"
cycles or "incomplete" counts from occuring). Also, I want/need
the async load, the application will load a new value, and move
on its merry way.

A count of 1 should not divide the clock, but "pass through" the
current clock. A count of 0 should disable the clock. Also, the
enable line should disable the counter (not implemented yet), and
upon "enable" (low to high transition), the counter should start
on the next clock edge. The output may go high on either a low
or high transition of the incomin clock (it may be up to 180 degree
out of phase wrt to the incoming clock).


So if the above is not possible (in general) on an edge basis, I
suppose I'll have to start clocking my design higher, and use full
cycles to do the various things?

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| 6512 - 98 Street |-----------------------------------------------------|
| Edmonton, AB T6G 1G3 | %SYSTEM-F-ANARCHISM, The OS has been overthrown |
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[John_H]

Comments inline below:

"Tobias Weingartner" <weingart@cs.ualberta.ca> wrote in message
news:slrnd0i2f5.jpc.weingart@irricana.cs.ualberta.ca...

In article <se6Od.8$iV.230@news-west.eli.net>, John_H wrote:
For synthesis, your registers should be in one "always" block. Also,
note
that few architectures allow both posedge clk and negedge clk triggering
for
a single register; the silicon is designed for a single edge. For those
architectures that do support dual clocks, the synthesis package usually
offers implementation templates in the online help.

Hmm... should the synthesis not be able to extrapolate into multiple
registers clocked on different edges, with the approriate logic added
to make it look "right"? I must be naiive... guess I go back and
try to figure it out explicitly.

I can't imagine how to mux multiple registers in a clean fashion to get the
"right" thing for a dual-edge system built with single edge registers. The
resources would more than double and the timing allowances reduce to less
than half. Not pretty all around.

If you have an asynchronous reset, a load is usually synchronous with
the
clock.

Something like:
always @(posedge clk or negedge nRst)
if( !nRst ) Count <= 0; // asynchronous
else if( !nLoad ) Count <= Data; // synchronous load - Data must be
synchronous to Clk
else if( Count==0 ) Count <= Data; // Reload
else Count <= Count -1;

If you want a faster clock (and the clock is continuous) consider the
DCM to
increase the input frequency.

Yikes, I'm not sure I understand 1/2 of this. Basically, I'm trying to
have a generic clock divider. Preferably something that will count edges,
not cycles. The behaviour I'm looking for are:

Async reset, reset all values to zero, inhibit any output.

Async reset is doable. I've typically been designing my FPGAs without a
system reset and any local resets I do need, I apply synchronously. The
reason I can get away without the async reset is that the FPGA programs to
known states in all the registers.

Async load, load into a staging register, and upon expiry of the
current counter, we use the new value (to try and prevent "short"
cycles or "incomplete" counts from occuring). Also, I want/need
the async load, the application will load a new value, and move
on its merry way.

The combination of the async reset and the async load isn't resource
friendly. Another thing to consider: when you release your asynchronous
load signal, what if some of your counter registers see the load but the
rest don't? Some of your register bits would decrement, some of them
wouldn't. You end up with a first count that can be much higher or lower
than what you expect. It would be better to latch your load value and
enable a synchronous load of this value only after it's know to be valid and
stable. This allows synchronous loading and no confusion on the first step
out of the load condition.

A count of 1 should not divide the clock, but "pass through" the
current clock. A count of 0 should disable the clock. Also, the
enable line should disable the counter (not implemented yet), and
upon "enable" (low to high transition), the counter should start
on the next clock edge. The output may go high on either a low
or high transition of the incomin clock (it may be up to 180 degree
out of phase wrt to the incoming clock).

The Xilinx FPGAs have "Digital Clock Managers" or "Delay Locked Loops" that
can double an incoming clock frequency. This allows hte posedge and negedge
of the original clock to be used to clock your logic by using the 2x clock's
rising edge. The input clock has to meet minimum frequencies and be
continuous for this to work without problems. Read up on the capabilities
in the Xilinx data sheets.

So if the above is not possible (in general) on an edge basis, I
suppose I'll have to start clocking my design higher, and use full
cycles to do the various things?

Full cycles are good cycles.

As for your general need: getting a lower speed "clock" from a higher speed
system clock, if you need it for FPGA internals rather than an external
clock signal, consider 1) running the logic at the system clock speed, 2)
providing the "slower" logic with a clock enable generated by your DCO
rather than a physical clock, and 3) specifying a "multi-cycle path" in the
timing constraints if you don't easily meet timing at the system clock rate.
The design technique allows a complete design to be synchrounous between
separate parts without problems introduced by clock skew. Clock skew is
often a problem if you generate a clock with registers and/or logic.

--

*---------------------------------------------------------------------------

-*

| Tobias Weingartner | Unix Guru, Admin, Systems-Dude, ...
|
| 6512 - 98 Street
|-----------------------------------------------------|
| Edmonton, AB T6G 1G3 | %SYSTEM-F-ANARCHISM, The OS has been overthrown
|

*---------------------------------------------------------------------------

-*

[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax