clock recovery from HDB3 data

[praveen]

hi all,

I have a 2.048 Mbps HDB3 data stream, now i should recover the clock
from this data stream. For this i am using 16.384 MHZ(8xbaud) clock.
First i detect the edges of the 2.048 Mbps data stream using 16.384
MHz(8xbaud)synchronously .The edges detected are used to reset a 3-bit
counter synchronously running at 16.384 Mbps.Now if i take the MSB of
the counter it will be of frequency 2.048 Mhz with the rising edge of
the recovered clock approximately at the center of the bit duration.

My problem is that the recoverd clock's rising edge will not be at the
center of the bit duration.I want the recovered clock's rising edge in
the middle of the bit duration . Should i increase the high frequency
clock to 16xBaud,
OR is there any other solution.

rgds,
praveen

 

praveen <praveen@cg-coreel.com> wrote:

hi all,

I have a 2.048 Mbps HDB3 data stream, now i should recover the clock
from this data stream. For this i am using 16.384 MHZ(8xbaud) clock.
First i detect the edges of the 2.048 Mbps data stream using 16.384
MHz(8xbaud)synchronously .The edges detected are used to reset a 3-bit
counter synchronously running at 16.384 Mbps.Now if i take the MSB of
the counter it will be of frequency 2.048 Mhz with the rising edge of
the recovered clock approximately at the center of the bit duration.

My problem is that the recoverd clock's rising edge will not be at the
center of the bit duration.I want the recovered clock's rising edge in
the middle of the bit duration . Should i increase the high frequency
clock to 16xBaud,
OR is there any other solution.

If the counter is assumed to be positive flank triggered. And you compare the
value of the counter to a preset value on the negative flank. You should be
able to grab the bit anywhere within each datavalidity range.
(Clock <= Counter equals Preset)

Btw, why isn't the recovered clocks's rising edge at the center ..?
Parasitic capatitance?

/Peter