Clock propagation

K

konstantink

Guest
Hi, everyone!

Please, somebody explain one thing. Regarding such code:

module top ( clk, reset, in_a, in_b, out );

input clk, reset, in_a, in_b;
output out;

reg out;

always @( posedge clk or negedge reset )
if ( reset == 1'b0 )
out <= 1'b0;
else
out <= ( clk ) ? in_a : in_b;

endmodule

The question is: is the output of the multiplexer regarded as clock
line and why?
And can you tell me when the clock propagation stops?

Thanks a lot!!!!
 
On 29 Mar 2007 07:26:34 -0700, "konstantink"
<slipkid@yandex.ru> wrote:

module top ( clk, reset, in_a, in_b, out );

input clk, reset, in_a, in_b;
output out;

reg out;

always @( posedge clk or negedge reset )
if ( reset == 1'b0 )
out <= 1'b0;
else
out <= ( clk ) ? in_a : in_b;

endmodule

The question is: is the output of the multiplexer regarded as clock
line and why?
And can you tell me when the clock propagation stops?
Click to expand...
This is VERY strange code.

At first glance it looks like a flip-flop. It has the right
structure, and the body of the always block looks
correct too. But then we find (clk) appearing as a term
in the logic! This is crazy. The "else" branch of your
if statement will execute only on (posedge clk), so
(assuming no X values) clk is definitely 1; so the
last line of code is equivalent to
out <= in_a;

A signal is regarded as a clock only if you use it
to clock some registers. You can do that with the
STANDARD clocked process arrangement.
In your example there is no "clock propagation"
of any kind. There is no multiplexer, for the
reasons I have described. And the output of the
circuit might be a clock, or it might not be,
depending on what you do with it elsewhere.

There are, I think, three possibilities here:

(1) You have a prof. who thinks he's being clever,
but in fact is just being confused. (It happens.)
(2) This is a "spot the deliberate mistake" homework
question, and I just gave you the right answer.
Shame on me.
(3) You have some colleagues who urgently need to
come on one of our Verilog training courses to learn
how to write sensible flip-flop models.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Mar 29, 10:26 am, "konstantink" <slip...@yandex.ru> wrote:
Hi, everyone!

Please, somebody explain one thing. Regarding such code:

module top ( clk, reset, in_a, in_b, out );

input clk, reset, in_a, in_b;
output out;

reg out;

always @( posedge clk or negedge reset )
if ( reset == 1'b0 )
out <= 1'b0;
else
out <= ( clk ) ? in_a : in_b;

endmodule

The question is: is the output of the multiplexer regarded as clock
line and why?
And can you tell me when the clock propagation stops?

Thanks a lot!!!!
Click to expand...

In your example, out <= in_a since clk is always "1" after the
posedge.
Synthesis tools will implement your block as a singe flip-flop.

-Alex
 
"Alex" <agnusin@gmail.com> wrote in message
news:1175180840.898677.189180@e65g2000hsc.googlegroups.com...
On Mar 29, 10:26 am, "konstantink" <slip...@yandex.ru> wrote:
Hi, everyone!

Please, somebody explain one thing. Regarding such code:

module top ( clk, reset, in_a, in_b, out );

input clk, reset, in_a, in_b;
output out;

reg out;

always @( posedge clk or negedge reset )
if ( reset == 1'b0 )
out <= 1'b0;
else
out <= ( clk ) ? in_a : in_b;

endmodule

The question is: is the output of the multiplexer regarded as clock
line and why?
And can you tell me when the clock propagation stops?

Thanks a lot!!!!


In your example, out <= in_a since clk is always "1" after the
posedge.
Synthesis tools will implement your block as a singe flip-flop.

-Alex
Click to expand...
That's assuming the synthesizer doesn't gack on the fact you are using the
clock as both clock and data.

Mike
 
On Mar 29, 11:57 am, "Mike Lewis" <some...@micrsoft.com> wrote:
"Alex" <agnu...@gmail.com> wrote in message

news:1175180840.898677.189180@e65g2000hsc.googlegroups.com...



On Mar 29, 10:26 am, "konstantink" <slip...@yandex.ru> wrote:
Hi, everyone!

Please, somebody explain one thing. Regarding such code:

module top ( clk, reset, in_a, in_b, out );

input clk, reset, in_a, in_b;
output out;

reg out;

always @( posedge clk or negedge reset )
if ( reset == 1'b0 )
out <= 1'b0;
else
out <= ( clk ) ? in_a : in_b;

endmodule

The question is: is the output of the multiplexer regarded as clock
line and why?
And can you tell me when the clock propagation stops?

Thanks a lot!!!!

In your example, out <= in_a since clk is always "1" after the
posedge.
Synthesis tools will implement your block as a singe flip-flop.

-Alex

That's assuming the synthesizer doesn't gack on the fact you are using the
clock as both clock and data.

Mike
Click to expand...
Synthesis tool indeed compiles design to 1 flop, but data pin of this
flop is connected to in_b ! In other words, synthesis tool assumes
that within always process clk = 0.

Morale: don't even try to mix clock with data ;)
 
On Mar 29, 2:51 pm, "Alex" <agnu...@gmail.com> wrote:
On Mar 29, 11:57 am, "Mike Lewis" <some...@micrsoft.com> wrote:



"Alex" <agnu...@gmail.com> wrote in message

news:1175180840.898677.189180@e65g2000hsc.googlegroups.com...

On Mar 29, 10:26 am, "konstantink" <slip...@yandex.ru> wrote:
Hi, everyone!

Please, somebody explain one thing. Regarding such code:

module top ( clk, reset, in_a, in_b, out );

input clk, reset, in_a, in_b;
output out;

reg out;

always @( posedge clk or negedge reset )
if ( reset == 1'b0 )
out <= 1'b0;
else
out <= ( clk ) ? in_a : in_b;

endmodule

The question is: is the output of the multiplexer regarded as clock
line and why?
And can you tell me when the clock propagation stops?

Thanks a lot!!!!

In your example, out <= in_a since clk is always "1" after the
posedge.
Synthesis tools will implement your block as a singe flip-flop.

-Alex

That's assuming the synthesizer doesn't gack on the fact you are using the
clock as both clock and data.

Mike

Synthesis tool indeed compiles design to 1 flop, but data pin of this
flop is connected to in_b ! In other words, synthesis tool assumes
that within always process clk = 0.

Morale: don't even try to mix clock with data ;)
Click to expand...

I would take this as the synthesizer being more knowledgable about
the hardware than the simulator. Take the template for a flip-flop
and you have a 2:1 mux selected on clock feeding the D. I would think
a
rising edge flop would need a significant negative hold time to
see the clock as "high" at the sampling edge. This sort of thing
(mixing active edge with active state) always bothered me when I
look at VHDL code like (clk'event and clk = 1). If there's an
event, clk is changing. So is it 1 or zero? Yes. At which edge?
Both.
 
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