Clock processing in a big project (Verilog Code)???

[Lee]

Dear all,

When I do a big project, I find it is hard to deal with clock. The
most of time when I did a big project is spent on clock control
signals.

For example, when writing a control unit, if I use synchronous memory,
I need to provide address and write/read signal before the arrival of
edge of clock. At the same time, address and write/read signals are
under control of the same clock. In this situation, anybody know how
to deal with this kind of problem?

When I write verilog code, I add some delay statement(i.e. #2). But
when I synthesize the verilog code, the delay statement is ignored. So
to use delay statement is not correct for RTL, right?

Another way I can use may be to write State Machine. But I am not sure
if there is any other good way to do that. Can anybody share with me?

Thanks,

 

[Jason Zheng]

Lee wrote:

Dear all,

When I do a big project, I find it is hard to deal with clock. The
most of time when I did a big project is spent on clock control
signals.

For example, when writing a control unit, if I use synchronous memory,
I need to provide address and write/read signal before the arrival of
edge of clock. At the same time, address and write/read signals are
under control of the same clock. In this situation, anybody know how
to deal with this kind of problem?

If you use the SRAM (on-chip), then you generate the address and r/w
signals between the clock ticks, everything should be fine. If you use
the SDRAM (external modules), you should write a memory controller,
because they usually run at different clock freq.

When I write verilog code, I add some delay statement(i.e. #2). But
when I synthesize the verilog code, the delay statement is ignored. So
to use delay statement is not correct for RTL, right?

Those delays are never part of the RTL.

Another way I can use may be to write State Machine. But I am not sure
if there is any other good way to do that. Can anybody share with me?

Try this (suppose you want a delay of 2 clock cycles):

old statement: always @ (w0 or w1) #2*clk_cycle w2 <= w1 ^ w0;
new statement: always @ (posedge clk) begin
w0_dly1 <= w0;
w0_dly2 <= w0_dly1;
w1_dly1 <= w1;
w1_dly2 <= w1_dly1;
end
assign w2 = w1_dly2 ^ w0_dly2;

Notice that the units of the delays can only be number of cycles (or 0.5
cycles). You shouldn't have to specify the actually timing delay (e.g. 5
ns), because each hardware is different in timing and there is no
precise way to guarantee something like 2ns delay at the design time.