Clock Process?

[Moikel]

Hey all,

I'm doing a project for college were I'm building a simple register
file. However, one part of the assignment has me confused. I need to
design a clock process which is high for 5ns and low for 25ns. I'm
using VHDL (of course).

Could somebody please help me with this?

Thanks a lot,

Moikel

 

[ALuPin@web.de]

You are talking about a Clock Process .
So what clock frequency are you using ?

Rgds
André

 

[Brandon]

Try this:
<SNIP>

clock_proc: process
begin
if (now = 0 ns) then
clk <= '0';
end if;
wait for 25 ns;
clk <= '1';
wait for 5 ns;
clk <= '0';

end process clock_proc;

</SNIP>

-Brandon

 

[Andy]

How about:

signal clock : std_logic := '0';

....

clock <= '1' after 25 ns when clock = '0'
else '0' after 5 ns when clock = '1';

Andy Jones

 

[anupam]

how about......

clockrocess
clock<='1';
wait for 5 ns;
clock <='0';
wait for 25 ns;
end process clock;


regards,
Anupam Jain

 

[ALuPin@web.de]

Moikel did not mention at all
if it is for simulation or for synthesis ...