S
Steve Ravet
Guest
I am using ISE 12.2 and targeting virtex6 LX760. When I take the netlist
through map I get the following error:
ERROR
lace:1153 - A clock IOB / BUFGCTRL clock component pair have been
found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The
clock
IOB component <SWCLKTCK> is placed at site <IOB_X0Y179>. The
corresponding
BUFGCTRL component <SWCLKTCK_ibuf> is placed at site <BUFGCTRL_X0Y2>. The
clock IO can use the fast path between the IOB and the Clock Buffer if a)
the
IOB is placed on a Global Clock Capable IOB site that has the fastest
dedicated path to all BUFGCTRL sites, or b) the IOB is placed on a Local
Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in
its
half of the device (TOP or BOTTOM). You may want to analyze why this
problem
exists and correct it. If this sub optimal condition is acceptable for
this
design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file
to
demote this message to a WARNING and allow your design to continue.
However,
the use of this override is highly discouraged as it may lead to very
poor
timing results. It is recommended that this error condition be corrected
in
the design. A list of all the COMP.PINs used in this clock placement rule
is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "SWCLKTCK" CLOCK_DEDICATED_ROUTE = FALSE; >
The clock net is assigned to pin AB37 via a LOC constraint in the .ncf file.
This corresponds to IOB_X0Y179 listed, which according to the package docs
is multi-region clock capable. There is no LOC for the BUFGCTRL, it was
inserted by the synthesis tool. So apparently the mapper selected the bad
location. I have a webcase open with xilinx on that question.
The workaround would seem to be to assign the BUFG to a compatible location,
but which ones are? In FPGA editor I have created nets from AB37 to BUFGs
in all four groups. It routed all of them, including to the one the mapper
complains about, but the nets all have 3-4ns of delay so I think they're on
general routing resources not clock nets.
I pulled up a different design with properly routed clock nets to compare
but I don't know enough about the internals to see the difference between
them.
So, in FPGA editor is there a way to restrict the routing of a net to only
be on clock nets? Is there a quicker way of finding out which IOBs and
BUFGs share fast paths?
thanks,
--steve
through map I get the following error:
ERROR
lace:1153 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The
clock
IOB component <SWCLKTCK> is placed at site <IOB_X0Y179>. The
corresponding
BUFGCTRL component <SWCLKTCK_ibuf> is placed at site <BUFGCTRL_X0Y2>. The
clock IO can use the fast path between the IOB and the Clock Buffer if a)
the
IOB is placed on a Global Clock Capable IOB site that has the fastest
dedicated path to all BUFGCTRL sites, or b) the IOB is placed on a Local
Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in
its
half of the device (TOP or BOTTOM). You may want to analyze why this
problem
exists and correct it. If this sub optimal condition is acceptable for
this
design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file
to
demote this message to a WARNING and allow your design to continue.
However,
the use of this override is highly discouraged as it may lead to very
poor
timing results. It is recommended that this error condition be corrected
in
the design. A list of all the COMP.PINs used in this clock placement rule
is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "SWCLKTCK" CLOCK_DEDICATED_ROUTE = FALSE; >
The clock net is assigned to pin AB37 via a LOC constraint in the .ncf file.
This corresponds to IOB_X0Y179 listed, which according to the package docs
is multi-region clock capable. There is no LOC for the BUFGCTRL, it was
inserted by the synthesis tool. So apparently the mapper selected the bad
location. I have a webcase open with xilinx on that question.
The workaround would seem to be to assign the BUFG to a compatible location,
but which ones are? In FPGA editor I have created nets from AB37 to BUFGs
in all four groups. It routed all of them, including to the one the mapper
complains about, but the nets all have 3-4ns of delay so I think they're on
general routing resources not clock nets.
I pulled up a different design with properly routed clock nets to compare
but I don't know enough about the internals to see the difference between
them.
So, in FPGA editor is there a way to restrict the routing of a net to only
be on clock nets? Is there a quicker way of finding out which IOBs and
BUFGs share fast paths?
thanks,
--steve