clock multiplier

[sunil]

Hi,
In my design a counter has to give 7 outputs in a single clock
period of main clock. So, i require a clock of 7 times of main clock
frequency. So, anybody knows how to get a clock of more frequency from
lesser frequency clock mail me. In brief I require a PROGRAM OF CLOCK
FREQUENCY MULTIPLIER. thanks for reading my mail.

 

[valentin tihomirov]

Many FPGAs include PLLs for this purpose. They are special devices. I wonder
if there is a generic VHDL code to do the job.

 

[Mike Treseler]

sunil wrote:

In my design a counter has to give 7 outputs in a single clock
period of main clock. So, i require a clock of 7 times of main clock

Consider a faster main clock.

-- Mike Treseler

 

[Ciaran]

If you are using Xilinx devices, there are Digital Clock Managers that
you can use (on the Virtex 2, Virtex 2 Pro, and Spartan 3 devices), or
PLLs on the Virtex device. You can find information on these at the
Xilinx website. (http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp).
Other devices may have different options.

There is no way to do this in generic VHDL, however, so you are going
to need a device that has one of these options.

Ciarán Hughes

 

[Sajan]

There is no way of desiging a clock multiplier in VHDL .
You will have to use a PLL to get the clock of required frequency.
Always the main clock has to be of the max frequency so that you
can divide the main clock as per the requirements by the design.



ciaran_hughes@yahoo.co.uk (Ciaran) wrote in message news:<c3375461.0402020102.2f3aeced@posting.google.com>...

If you are using Xilinx devices, there are Digital Clock Managers that
you can use (on the Virtex 2, Virtex 2 Pro, and Spartan 3 devices), or
PLLs on the Virtex device. You can find information on these at the
Xilinx website. (http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp).
Other devices may have different options.

There is no way to do this in generic VHDL, however, so you are going
to need a device that has one of these options.

Ciarán Hughes

 

[jussi l]

hello,

well, strictly speaking that is not quite the truth. You could easily
implement delay lines from the original clock and then combine them in some
logical manner to create faster frequencies (on FPGA or ASIC). Such designs
are ofcourse highly unreliable and will have a create jitter with them, but
with small frequencies and no-commercial design they can be adequate.
wouldn't use them though

regards,
juza


"Sajan" <s_sajan_s@yahoo.com> wrote in message
news:d244d444.0402022003.2c2d5259@posting.google.com...

There is no way of desiging a clock multiplier in VHDL .
You will have to use a PLL to get the clock of required frequency.
Always the main clock has to be of the max frequency so that you
can divide the main clock as per the requirements by the design.



ciaran_hughes@yahoo.co.uk (Ciaran) wrote in message
news:<c3375461.0402020102.2f3aeced@posting.google.com>...
If you are using Xilinx devices, there are Digital Clock Managers that
you can use (on the Virtex 2, Virtex 2 Pro, and Spartan 3 devices), or
PLLs on the Virtex device. You can find information on these at the
Xilinx website.
(http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp).
Other devices may have different options.

There is no way to do this in generic VHDL, however, so you are going
to need a device that has one of these options.

Ciarán Hughes

 

[Eric Smith]

s_sajan_s@yahoo.com (Sajan) writes:

There is no way of desiging a clock multiplier in VHDL .

Certainly you can design a clock multiplier in VHDL. It's not even
particularly difficult. But it won't be synthesizable.