clock multiplication DQPSK

hi

I've designed a DQPSK modem and my problem is to produce the clock bit
from the symbol clock with
clock_bit = 2 * clock_symbol


how to do this in VHDL, I don't find ideas...


the major problem is that the symbol clock is produce from a 88 MHz
sampling clock, so there is a 11 ns jitter on this clock, the symbol
clock is 2 MHz and I would like to produce a 4 MHz clock...


I cannot only delay the symbol clock by half period and the XORED...


I think to count how many samples I've got and then reproduced this
counter and divided by 4 to produce the clock bit


if you have already designed this help could be fine...


thanks