Clock generation

[Patrik Eriksson]

Hi,

I would like to generate a clock from a refclk according to the
following function:

clk = refclk*(64/66)

I will implement this function in an VirtexII Pro FPGA and my first
approach is to divide the refclk by 3 in logic and then use a DCM to
multiply with 32/11.

clk = refclk*(1/3)*(64/22)
clk = refclk/3*(32/11)

Will this work? The frequencies has to be locked to each other.


------
Patrik Eriksson

 

[Vladislav Muravin]

what is your refclk frequency?.

"Patrik Eriksson" <no.spam@netinsight.net> wrote in message
news:40f69fd4$1@fnewsa.telia.net...

Hi,

I would like to generate a clock from a refclk according to the
following function:

clk = refclk*(64/66)

I will implement this function in an VirtexII Pro FPGA and my first
approach is to divide the refclk by 3 in logic and then use a DCM to
multiply with 32/11.

clk = refclk*(1/3)*(64/22)
clk = refclk/3*(32/11)

Will this work? The frequencies has to be locked to each other.


------
Patrik Eriksson

 

[Allan Herriman]

On Thu, 15 Jul 2004 15:09:12 -0400, "Vladislav Muravin"
<xfilex2003@hotmail.com> wrote:

what is your refclk frequency?.

64B/66B coding is used in 10G Ethernet. I guess this is what the OP
is using.
One would assume that the output frequency would be 644.53125MHz or
perhaps 161.1328MHz or so, so refclk would be 625 or 156.25MHz.

Jitter is really important for this sort of design. I recommend that
the OP uses an external analog PLL to generate the clock.

Regards,
Allan.

"Patrik Eriksson" <no.spam@netinsight.net> wrote in message
news:40f69fd4$1@fnewsa.telia.net...
Hi,

I would like to generate a clock from a refclk according to the
following function:

clk = refclk*(64/66)

I will implement this function in an VirtexII Pro FPGA and my first
approach is to divide the refclk by 3 in logic and then use a DCM to
multiply with 32/11.

clk = refclk*(1/3)*(64/22)
clk = refclk/3*(32/11)

Will this work? The frequencies has to be locked to each other.


------
Patrik Eriksson

 

[Vladislav Muravin]

as far as i remember, if you are using a CLKIN input of DCM with that high
frequency clock,
its input clock should have 50 +/- 5% duty cycle.
a division by 3 using counter would not give that.

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:v4hef0pkh54lg6jgjs0sojpi8qju9sm95q@4ax.com...

On Thu, 15 Jul 2004 15:09:12 -0400, "Vladislav Muravin"
xfilex2003@hotmail.com> wrote:

what is your refclk frequency?.

64B/66B coding is used in 10G Ethernet. I guess this is what the OP
is using.
One would assume that the output frequency would be 644.53125MHz or
perhaps 161.1328MHz or so, so refclk would be 625 or 156.25MHz.

Jitter is really important for this sort of design. I recommend that
the OP uses an external analog PLL to generate the clock.

Regards,
Allan.

"Patrik Eriksson" <no.spam@netinsight.net> wrote in message
news:40f69fd4$1@fnewsa.telia.net...
Hi,

I would like to generate a clock from a refclk according to the
following function:

clk = refclk*(64/66)

I will implement this function in an VirtexII Pro FPGA and my first
approach is to divide the refclk by 3 in logic and then use a DCM to
multiply with 32/11.

clk = refclk*(1/3)*(64/22)
clk = refclk/3*(32/11)

Will this work? The frequencies has to be locked to each other.


------
Patrik Eriksson