Clock Generation from Asynchronous Data Stream

[Daniel Gowans]

Hello all...

I am using a Xilinx Vitex II FPGA to unwrap a G.709 signal (OTU1) and
output the underlying STM-16 (or other CBR2G5 signal).

The synchronous payload case is easy- I can use a DCM to generate a clock
from the incoming data's recovered clock, and use that to clock out the
data from an asynchronous FIFO filled by the unwrapping logic.

However, the asynchronous payload case seems undoable to me within the
FPGA. Since the asynchronous payload could vary by +/- 65 ppm from the
equivalent synchronous payload, I need to use the asynchronous data to
generate a new clock, or use FIFO level measurement to fine tune the
frequency of the outgoing clock. If I try to use the clock derived from
the input clock, the FIFO could at worst start to over/underflow after
about 1/10th second.

Lastly, if it really can't be done in an FPGA, what type of part could be
used in tandem that would allow clock generation from a data stream that is
accompanied by a valid signal?

Thanks!

 

[John_H]

If you're using the recovered clock in an ITU compliant system requiring
very small jitter, take a look at the icst.com clock recovery products to
see about filtering a telecomm clock. They have SAW-based products that can
keep jitter within spec.

A Numerically Controlled Oscillator can produce your desired STM-16 payload
frequency when you supply frequency adjustments based on your FIFO depth.
That NCO can either generate a digital sinusoid and use a D/A to generate a
sine wave at your desired output frequency or the MSbit of the NCO can be
used to produce a jittered clock that is cleaned up by a PLL like the ones I
mentioned from icst.com; less stringent jitter requirements need less
expensive chips.

If you only need to generate synchronous data and clock, don't bother
recovering the clock but send out a gated clock with your gated data.

So - what do you *need*?


"Daniel Gowans" <chlump@yahoo.com> wrote in message
news:Xns94EC73A2829D9chlumpyahoocom@198.60.22.31...

Hello all...

I am using a Xilinx Vitex II FPGA to unwrap a G.709 signal (OTU1) and
output the underlying STM-16 (or other CBR2G5 signal).

The synchronous payload case is easy- I can use a DCM to generate a clock
from the incoming data's recovered clock, and use that to clock out the
data from an asynchronous FIFO filled by the unwrapping logic.

However, the asynchronous payload case seems undoable to me within the
FPGA. Since the asynchronous payload could vary by +/- 65 ppm from the
equivalent synchronous payload, I need to use the asynchronous data to
generate a new clock, or use FIFO level measurement to fine tune the
frequency of the outgoing clock. If I try to use the clock derived from
the input clock, the FIFO could at worst start to over/underflow after
about 1/10th second.

Lastly, if it really can't be done in an FPGA, what type of part could be
used in tandem that would allow clock generation from a data stream that
is
accompanied by a valid signal?

Thanks!

 

[Daniel Gowans]

Thanks for your help, John. Unfortunately, generating synchronous
data and clock isn't really an option, as this data is going to be
sent out optically. Therefore it has to be within spec and the
frequency must meet jitter very stringently. Unfortunately our
current hardware platform cannot be modified- I only have power to
modify the FPGA.

However, new hardware is in the design stages. Most likely support
for the asynchronous case will have to be included in the next
platform. It will be using an architecture such as that which you
described. Thanks for your help!

"John_H" <johnhandwork@mail.com> wrote in message news:<JM8qc.5$zR5.133@news-west.eli.net>...

If you're using the recovered clock in an ITU compliant system requiring
very small jitter, take a look at the icst.com clock recovery products to
see about filtering a telecomm clock. They have SAW-based products that can
keep jitter within spec.

A Numerically Controlled Oscillator can produce your desired STM-16 payload
frequency when you supply frequency adjustments based on your FIFO depth.
That NCO can either generate a digital sinusoid and use a D/A to generate a
sine wave at your desired output frequency or the MSbit of the NCO can be
used to produce a jittered clock that is cleaned up by a PLL like the ones I
mentioned from icst.com; less stringent jitter requirements need less
expensive chips.

If you only need to generate synchronous data and clock, don't bother
recovering the clock but send out a gated clock with your gated data.

So - what do you *need*?


"Daniel Gowans" <chlump@yahoo.com> wrote in message
news:Xns94EC73A2829D9chlumpyahoocom@198.60.22.31...
Hello all...

I am using a Xilinx Vitex II FPGA to unwrap a G.709 signal (OTU1) and
output the underlying STM-16 (or other CBR2G5 signal).

The synchronous payload case is easy- I can use a DCM to generate a clock
from the incoming data's recovered clock, and use that to clock out the
data from an asynchronous FIFO filled by the unwrapping logic.

However, the asynchronous payload case seems undoable to me within the
FPGA. Since the asynchronous payload could vary by +/- 65 ppm from the
equivalent synchronous payload, I need to use the asynchronous data to
generate a new clock, or use FIFO level measurement to fine tune the
frequency of the outgoing clock. If I try to use the clock derived from
the input clock, the FIFO could at worst start to over/underflow after
about 1/10th second.

Lastly, if it really can't be done in an FPGA, what type of part could be
used in tandem that would allow clock generation from a data stream that
is
accompanied by a valid signal?

Thanks!