Clock gating

N

niks

Guest
Hi,
Can anyone tell me how clock gating checks are done ? It would be
helpfull if you can give an example and then explain it because ptug
has the definitions. If there is min path violation for clock gating
check then do we remove it by inserting a buffer in enable path or
something else?

Thanks,
Nikhil
 
niks wrote:

Can anyone tell me how clock gating checks are done ? It would be
helpfull if you can give an example and then explain it because ptug
has the definitions. If there is min path violation for clock gating
check then do we remove it by inserting a buffer in enable path or
something else?
Something else: synchronous clock enables.
 

Welcome to EDABoard.com

Sponsor

Back
Top