Clock domains

[Beregnyei Balazs]

Hi,

I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20 MHz.
My problem: data transport between domains create deadlock.
(When I use the same clock in all domains, this send/receive primitive
works fine, but I need different clocks...)
Can somebody help me? URL, FAQ, RTFM?

Thanks,
BB

// send @ 33 MHz
data_reg = 4;
data_ready <= data_ready ^ 1;

// receive @ 20 MHz
case (state)
0: if (data_ready != last_data_ready)
begin
last_data_ready = last_data_ready ^ 1;
state <= 1;
end
1: // READ data_reg

 

[Patrik Eriksson]

Beregnyei Balazs wrote:

Hi,

I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20 MHz.
My problem: data transport between domains create deadlock.
(When I use the same clock in all domains, this send/receive primitive
works fine, but I need different clocks...)
Can somebody help me? URL, FAQ, RTFM?

Thanks,
BB

// send @ 33 MHz
data_reg = 4;
data_ready <= data_ready ^ 1;

// receive @ 20 MHz
case (state)
0: if (data_ready != last_data_ready)
begin
last_data_ready = last_data_ready ^ 1;
state <= 1;
end
1: // READ data_reg

I don't exactly know what you want to do but maybe this could be helpful.
Read this: At www.xilinx.com -> TechXclusive -> "Moving Data Across
Asynchronous Clock Boundaries" by Peter Alfke

Patrik Eriksson

 

[Jonathan Bromley]

"Beregnyei Balazs" <bereg@impulzus.sch.bme.hu> wrote in
message newsine.LNX.4.58.0401071544160.10548@impulzus.sch.bme.hu...

I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20
MHz.
My problem: data transport between domains create deadlock.
(When I use the same clock in all domains, this send/receive primitive
works fine, but I need different clocks...)
Can somebody help me? URL, FAQ, RTFM?

Your circuit is (approximately) Weinstein's Flancter.
Read the details in this URL:
http://www.xilinx.com/xcell/xl37/xcell37_54.pdf

// send @ 33 MHz
data_reg = 4;
data_ready <= data_ready ^ 1;

// receive @ 20 MHz
case (state)
0: if (data_ready != last_data_ready)
begin
last_data_ready = last_data_ready ^ 1;
state <= 1;
end
1: // READ data_reg

A couple of questions:

1) did you remember to initialise data_ready and
last_data_ready?

2) did you stop the 33MHz side from sending, by having
it look at the value of last_data_ready? If you send
two values, then data_ready will toggle twice and the
20MHz side will not see it.

HTH
--

Jonathan Bromley, Consultant

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