Clock division by 2

[Parthav]

Hi.
I need to have two clocks in my system,one is simple clock and another
is the half of that clock frequency.

I have implemented already but i have two warnings? So i m confused
that whether this can creat problems with actual design or not?

I m giving my code for the referrence along with the two warnings that
have been displayed by Xilinx ISE 7.1i


module newclk(op,clk);
input clk;
output op;
reg op;
reg [1:0] temp = 2'b00;
always @ (posedge clk)
begin
temp <= temp +1;
if(temp == 2'b00)
begin
op<=1'b0;
end
else if(temp == 2'b10)
begin
op<=1'b0;
end
else
begin
op <=1'b1;
end
end
endmodule

WARNINGS are::

WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <temp>.
WARNING:Xst:1291 - FF/Latch <temp_1> is unconnected in block <newclk>.

So friends could you do something for me? Another reason is that i m
using this half frequency in some of my modules of the design. So is
there any problem while using that?

Thanks & Regards...

Parthav

 

[Jerome]

Hi,

Your implementation is quite complicated.
always @(posedge clk or posedge rst)
begin
if (rst) op <= 1'b0;
else op <= ~op;
end

rgds.
jerome.

Parthav a écrit :

Hi.
I need to have two clocks in my system,one is simple clock and another
is the half of that clock frequency.

I have implemented already but i have two warnings? So i m confused
that whether this can creat problems with actual design or not?

I m giving my code for the referrence along with the two warnings that
have been displayed by Xilinx ISE 7.1i


module newclk(op,clk);
input clk;
output op;
reg op;
reg [1:0] temp = 2'b00;
always @ (posedge clk)
begin
temp <= temp +1;
if(temp == 2'b00)
begin
op<=1'b0;
end
else if(temp == 2'b10)
begin
op<=1'b0;
end
else
begin
op <=1'b1;
end
end
endmodule

WARNINGS are::

WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <temp>.
WARNING:Xst:1291 - FF/Latch <temp_1> is unconnected in block <newclk>.

So friends could you do something for me? Another reason is that i m
using this half frequency in some of my modules of the design. So is
there any problem while using that?

Thanks & Regards...

Parthav

 

[Chris F Clark]

In addition to being far more complicated than needed as per Jerome's
comment, you do somethings I find quite questionable in general. I
don't know Xilinx specifically, so I can't comment on the exact
warnings. However, let me point out one thing you do that seems to
be a bad coding style.

temp <= temp +1;
if(temp == 2'b00)
begin
....
end

The if statement will use the previous value of temp not the new
value. Non-blocking assignments are just that, non-blocking, which
means the value doesn't change until "later". Therefore, I would
suggest that it is generally bad form to have a non-blocking
assignment to a variable followed by uses of the variable, unless it
is otherwise unavoidable, e.g. in the swap idiom. The naive reader of
your code is going to expect temp to have the updated value in the
subesquent statements and it won't. It would be simpler to understand
if you wrote the code like, I show below. Then, the naive reading of
the code matches the actual behavior.

if(temp == 2'b00)
begin
....
end
temp <= temp +1;

If you meant to use the new value of temp in your if-statement, you
need to use a blocking assign.

Along the same lines, the use of a name like temp, implies a
temporary, transient value. Your code uses temp as a state
device--that may be the cause of the Xilinx warnings, since it is a
slightly "strange" state device. If you mean it to keep its value
from one execution of the block to the next, you should pick a better
name, perhaps something like divide_by_2_clock_state. Of course, if
you use Jerome's simple/obvious clock divider you don't need this
variable in this case, but you might need it in some other logic. In
that case, using a short non-descript name like temp doesn't help the
reader of your code understand what you are trying to do.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

[gabor]

Parthav,

These warnings are not errors. Basically you have a two-bit
counter temp[1:0], but only the least significant bit of this
counter is ever used. The synthesis rightly picked out the
fact that the behavior for temp == 1x is the same as for temp == 0x
where x is the same for the two cases.

Since you're only trying to divide by two, this is only to be expected.
You can ignore the warnings or simplify your code as suggested in
the other posts.

The warnings are not very illuminating. "unconnected" in this case
means the bit drives no loads, not that it has no source.

Good luck,
Gabor

Parthav wrote:

Hi.
I need to have two clocks in my system,one is simple clock and another
is the half of that clock frequency.

I have implemented already but i have two warnings? So i m confused
that whether this can creat problems with actual design or not?

I m giving my code for the referrence along with the two warnings that
have been displayed by Xilinx ISE 7.1i


module newclk(op,clk);
input clk;
output op;
reg op;
reg [1:0] temp = 2'b00;
always @ (posedge clk)
begin
temp <= temp +1;
if(temp == 2'b00)
begin
op<=1'b0;
end
else if(temp == 2'b10)
begin
op<=1'b0;
end
else
begin
op <=1'b1;
end
end
endmodule

WARNINGS are::

WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <temp>.
WARNING:Xst:1291 - FF/Latch <temp_1> is unconnected in block <newclk>.

So friends could you do something for me? Another reason is that i m
using this half frequency in some of my modules of the design. So is
there any problem while using that?

Thanks & Regards...

Parthav

 

[Ron]

Parthav wrote:

Hi.
I need to have two clocks in my system,one is simple clock and another
is the half of that clock frequency.


How about something like this:

module newclk(op,clk);
input clk;
output reg op;
reg [1:0] cnt;
assign op = cnt[1];
always @ (posedge clk)
cnt<= cnt+1;
endmodule