clock divider

[FP]

How do I design a clock divider without using initial conditions. I
designed once using initial values but they dont mean anything in
synthesis.

Thanks in advance for your help

 

[KJ]

On Jun 2, 4:10 pm, FP <FPGA.unkn...@gmail.com> wrote:

How do I design a clock divider without using initial conditions.

With a reset signal.

I designed once using initial values but they dont mean anything in
synthesis.

If your targetted part has a specified power up state and the tools

that you choose to use support initial values then initial values will
work just fine.

KJ