Clock Divider in a 22V10

[sam]

Hello all:


I have a 6.144Mhz crystal and I am trying to
generate the 9600*16 ~ 154k clock needed by the
8251 UART and the ~ 1Mhz system clock.

I dont want to use the 74ls* series ripple
counters and I have a bunch of 22v10 PAL chips
lying around.

I have been thinking about how best to do this,
using what I have.

Basically I need to divide the 6.144Mhz by 40.
First by 5 to realize the system clock, then by
8 to realize the UART baud clock.

With the 22v10 I could set aside two 3 bit
"registered" outputs for a GLITCH FREE
synchronous counter ... But I would need the
output of one to drive the other ... and I
dont see how I can do this when they all
share a common CLK input.

By the way I also have a bunch of 74ls112 dual
J/K flip flops lying around (about 25). I
thought I might use that along with the 22v10'
to realize my clock divider.

Any ideas?

 

[John Larkin]

On Fri, 11 Feb 2005 17:12:36 GMT, sam <sam@here.com> wrote:

Hello all:


I have a 6.144Mhz crystal and I am trying to
generate the 9600*16 ~ 154k clock needed by the
8251 UART and the ~ 1Mhz system clock.

I dont want to use the 74ls* series ripple
counters and I have a bunch of 22v10 PAL chips
lying around.

I have been thinking about how best to do this,
using what I have.

Basically I need to divide the 6.144Mhz by 40.
First by 5 to realize the system clock, then by
8 to realize the UART baud clock.

With the 22v10 I could set aside two 3 bit
"registered" outputs for a GLITCH FREE
synchronous counter ... But I would need the
output of one to drive the other ... and I
dont see how I can do this when they all
share a common CLK input.

Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."

John

 

[Ken Smith]

In article <pssp01940r9trdauq7epc8l4fsee71c8ti@4ax.com>,
John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
[...]

Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."

I think John meant this but it isn't clear so:

If you make the decoded output from the fast section registered. you get
the combined logic without adding a lot of delay.

The whole thing is well withing the 22V10s reach.

--
--
kensmith@rahul.net forging knowledge

 

[tlbs]

Back in 1988, I had to make a large counter in a CPLD. I used Altera's
EP610, which is similar to the 22V10's. Altera's flops could be
switched between "D" and "T" type flops, so making a synchronous ripple
counter was a simple task. I don't know if the 22V10's have that
option to switch flops to "T"-type. If they don't you could always
configure them as "T"-type in the feedback terms and that would make
the counter logic easier, anyway. I don't see a problem running at 6
MHz to generate a 154 kHz clock -- that's only a 6-bit counter.

 

[Meindert Sprang]

"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:0m5q01t63g4fmadvvtfu79aeu71plhfm1q@4ax.com...

Counters *are* a pain in a 22V10;

Nah, I used to use Tango PLD.

Below is an example of an up/down counter:

module(in HOLD, CLK; reg io D7..0; io UP; out WR)
{
/* setup some stuff */
group D[D7..0];
D[].oe = HI;
D[].ck = CLK;
D[].aclr = 0;
D[].pre = 0;
UP.oe = 1;
WR.oe = HI;

if (HOLD==0)
{
if (UP.fb) D[]++; /* D is counter, count up */
else D[]--; /* or count down, voila... */
WR = CLK;
}
else
{
D[] = D[];
WR = HI;
}

Meindert

 

[Meindert Sprang]

"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:1gbq015ibg617j0nrmnj227cllfkphlj5j@4ax.com...

Yeah, that's a lot easier than APEEL, where you have to grind out the
product terms.


" NOW DO THE COUNTER BITS...

MA1 = /MA1 * /MAX

MA2 = /MA2 * MA1 * /MAX
+ MA2 * /MA1 * /MAX

MA3 = /MA3 * MA2 * MA1 * /MAX
+ MA3 * /MA2 * /MAX
+ MA3 * /MA1 * /MAX

<snip>

Ha, and exactly that could be distilled from the output of TangoPLD

So in a 22V10 the product terms get burned up fast as the counter gets
longer, no matter how you compile it.

Correct, however my example *was* made for a 22V10. And it worked (8 bits
wide).

Meindert

 

[Glenn Gundlach]

Well sir, I beg to differ a little. My TV remote transcoder boards are
in transit from Advanced Circuits. It uses a 68HC908JK3 to listen to
the IR receiver. I needed a 38kHz for pulsing the IR transmit LED. With
the 32MHz osc, thats divide by 840 so I have an 'F163 to prescale by 15
to
2.133MHz and then do the rest of the counting and gating in a 22V10
(38095 Hz is close enough). It divides by 56 with a 50/50 duty cycle by
counting from 4 to 60 in the 6 bit counter and then the IRQ to the
controller and the gating with the transmit, also from the controller.
The 22V10 is just dandy for this in spite of being a power hog. I can
live with it. Using MSI counters would have been more tedious to work
out and would have used more packages. Gating changes in a GAL are
easily reprogrammed.
GG

 

[Ken Smith]

In article <420d1f5f$1@clear.net.nz>,
Jim Granville <no.spam@designtools.co.nz> wrote:
[...]

Good software for 22V10 code is Atmel's free WinCUPL.

IMO: ICT's place is better.

--
--
kensmith@rahul.net forging knowledge