Clock distribution for ADC and jitter

[Benjamin Couillard]

Hi everyone,

I've got a question regarding clocks and jitter. Let's say I have 2
ADCs that need an input clock of 80 MHz. have an 80 MHz low-jitter
crystal connected to an FPGA and then I use the FPGA as a clock buffer
and I output the 2 clocks from the FPGA to the 2 ADCs.

We know that clock jitter is critical for high-speed ADCs, so I would
like to know, is it a good way to distribute a clock to two ADCs? Will
the FPGA add jitter? Assume I do not use any PLL in my design, the
clock goes straight from the input pin to the 2 output pins on global
routing resources. I've looked at Altera datasheet and it is not
really clear what jitter would be added by the FPGA, the only place
jitter is mentionned is for PLLs not for clock routing.

Thanks

 

[Tim Wescott]

On Fri, 16 Dec 2011 07:59:18 -0800, Benjamin Couillard wrote:

Hi everyone,

I've got a question regarding clocks and jitter. Let's say I have 2 ADCs
that need an input clock of 80 MHz. have an 80 MHz low-jitter crystal
connected to an FPGA and then I use the FPGA as a clock buffer and I
output the 2 clocks from the FPGA to the 2 ADCs.

We know that clock jitter is critical for high-speed ADCs, so I would
like to know, is it a good way to distribute a clock to two ADCs? Will
the FPGA add jitter? Assume I do not use any PLL in my design, the clock
goes straight from the input pin to the 2 output pins on global routing
resources. I've looked at Altera datasheet and it is not really clear
what jitter would be added by the FPGA, the only place jitter is
mentionned is for PLLs not for clock routing.

I was once in a communications circuit seminar with a bunch of FPGA types
and I asked some question about doing something that depended on the FPGA
clocking being low jitter -- I got laughed at.

Since then I've remembered that whenever I needed to depend on clocks
remaining pristine as the wend their ways through FPGA logic.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

 

[Ed McGettigan]

On Dec 16, 7:59 am, Benjamin Couillard <benjamin.couill...@gmail.com>
wrote:

Hi everyone,

I've got a question regarding clocks and jitter. Let's say I have 2
ADCs that need an input clock of 80 MHz. have an 80 MHz low-jitter
crystal connected to an FPGA and then I use the FPGA as a clock buffer
and I output the 2 clocks from the FPGA to the 2 ADCs.

We know that clock jitter is critical for high-speed ADCs, so I would
like to know, is it a good way to distribute a clock to two ADCs? Will
the FPGA add jitter? Assume I do not use any PLL in my design, the
clock goes straight from the input pin to the 2 output pins on global
routing resources. I've looked at Altera datasheet and it is not
really clear what jitter would be added by the FPGA, the only place
jitter is mentionned is for PLLs not for clock routing.

Thanks

The quality of the ADC sampling will be better if you distribute the
clock from the original 80 MHz source to both ADCs and the FPGA with a
dedicated clock buffer.

Ed McGettigan
--
Xilinx Inc.

 

[Hal Murray]

I was once in a communications circuit seminar with a bunch of FPGA types
and I asked some question about doing something that depended on the FPGA
clocking being low jitter -- I got laughed at.

I'd expect troubles from noise on the power rails if the FPGA is
running other logic. How good/bad are they if they are only
acting as a clock switcher/divider?

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Benjamin Couillard]

Thank you both for your answers.

I'll put a dedicated clock buffer!

 

[Andy]

Though not a comment on jitter per se, most FPGA architectures do not
support directly connecting a global net to an output; they usually
have to go through some amount of local routing to get from the global
net to the output. The choice of local routing resources (and
therefore propagation/skew between multiple outputs) is dependent upon
what other signals are competing for those resources. You can try to
manually route them, and lock that down (ugly), but I have run into
issues where the same routing paths and delays from the global net to
the output (input of the output buffer) were not present on each
output.

One solution to this output skew problem is to use two DDR output FFs,
both clocked from the global clock net, and hard-wired to '1' on the
rising edge data input and '0' on the falling edge data input. You may
need attributes or have to instantiate the DDR primitive to keep
synthesis from trying to optimize it out. This way you are using
dedicated global routing to get to the output FF, and dedicated
circuitry from there to the pad, resulting in predictable, repeatable
delay and skew between outputs.

Like I said, this does not do anything (good) for jitter, but it does
solve skew problems, at least in a predictable, repeatable way.

Andy

 

[glen herrmannsfeldt]

Andy <jonesandy@comcast.net> wrote:

Though not a comment on jitter per se, most FPGA architectures do not
support directly connecting a global net to an output; they usually
have to go through some amount of local routing to get from the global
net to the output. The choice of local routing resources (and
therefore propagation/skew between multiple outputs) is dependent upon
what other signals are competing for those resources.

This is all true, but the question is jitter. If you only have one ADC,
then skew isn't usually a problem. Jitter can be.

I haven't seen so much discussion on sources of jitter within the
FPGA, or how it compares to other methods.

-- glen

 

[Andy]

On Dec 21 2011, 3:07 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:

This is all true, but the question is jitter.  If you only have one ADC,
then skew isn't usually a problem.  Jitter can be.

The OP stated he had 2 ADCs. Skew can be a problem with 2 ADCs,
depending upon the application.

Andy