Clock Delay

[jjlindula@hotmail.com]

Hello, I just started learning Verilog and I have a quick question. I
want to know why there would be a delay if I simply pass a clock input
into a module and the pass it out of the module. For example:


module passClock(input clock_in, output clock_out)


clock_out = clock_in;


endmodule

When I run this through the Simulator in Quartus I notice a slight
phase shift in the output clock. Any ideas why there is a difference
in clocks?

Thanks,
joe

 

[q-rious]

On Mar 26, 8:00 am, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote:

Hello, I just started learning Verilog and I have a quick question. I
want to know why there would be a delay if I simply pass a clock input
into a module and the pass it out of the module. For example:

module passClock(input clock_in, output clock_out)

clock_out = clock_in;

endmodule

When I run this through the Simulator in Quartus I notice a slight
phase shift in the output clock. Any ideas why there is a difference
in clocks?

Thanks,
joe

Did the above code really compile? If it was slightly different code,
may be there was something like a '#' symbol somewhere in the code?

 

[asicbaba]

On Mar 26, 8:00 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote:

Hello, I just started learning Verilog and I have a quick question. I
want to know why there would be a delay if I simply pass a clock input
into a module and the pass it out of the module. For example:

module passClock(input clock_in, output clock_out)

clock_out = clock_in;

endmodule

When I run this through the Simulator in Quartus I notice a slight
phase shift in the output clock. Any ideas why there is a difference
in clocks?

Thanks,
joe

some simulation tools, use Delta delay in simulation, i guess what u
see is 1 unit of that delay between input and output in phase.

 

[jjlindula@hotmail.com]

On Mar 26, 8:10 pm, asicbaba <asicb...@gmail.com> wrote:

On Mar 26, 8:00 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com
wrote:



Hello, I just started learning Verilog and I have a quick question. I
want to know why there would be a delay if I simply pass a clock input
into a module and the pass it out of the module. For example:

module passClock(input clock_in, output clock_out)

clock_out = clock_in;

endmodule

When I run this through the Simulator in Quartus I notice a slight
phase shift in the output clock. Any ideas why there is a difference
in clocks?

Thanks,
joe

some simulation tools, use Delta delay in simulation, i guess what u
see is 1 unit of that delay between input and output in phase.

Thanks for responding to my post. I no longer route clocks in and out
of a module as listed above.
joe

 

On Mar 26, 11:00 am, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote

module passClock(input clock_in, output clock_out)

clock_out = clock_in;

endmodule

When I run this through the Simulator in Quartus I notice a slight
phase shift in the output clock. Any ideas why there is a difference
in clocks?

I assume that you actually have the keyword "assign" before that
assignment statement, making it a zero-delay continuous assignment.

Since it is zero-delay, both signals should transition at the same
simulation time. However, clock_out will probably transition at a
later point during that simulation time. When clock_in transitions,
all of its fanout is scheduled to execute, including the continuous
assignment to clock_out. You will not see a transition on clock_out
until after the continuous assignment has executed. So other fanout
of clock_in may execute before clock_out has transitioned.

 

[jjlindula@hotmail.com]

On Mar 27, 9:48 am, sh...@cadence.com wrote:

On Mar 26, 11:00 am, "jjlind...@hotmail.com" <jjlind...@hotmail.com
wrote



module passClock(input clock_in, output clock_out)

clock_out = clock_in;

endmodule

When I run this through the Simulator in Quartus I notice a slight
phase shift in the output clock. Any ideas why there is a difference
in clocks?

I assume that you actually have the keyword "assign" before that
assignment statement, making it a zero-delay continuous assignment.

Since it is zero-delay, both signals should transition at the same
simulation time. However, clock_out will probably transition at a
later point during that simulation time. When clock_in transitions,
all of its fanout is scheduled to execute, including the continuous
assignment to clock_out. You will not see a transition on clock_out
until after the continuous assignment has executed. So other fanout
of clock_in may execute before clock_out has transitioned.

Hello, yes you are right, I am using the keyword 'assign'. Thanks for
responding to my post.
joe