clock connection logic ?

[aaaaaa]

Hi guyes,
I have 21 input clock signal and 21 correwsponding los signals . If a
clock (out of these 21) is not coming the los signal of that clock will
come as "high".
CPU can write the priority of these 21 clocks thru chip_select add and
data bus. I want to connect the highest priority clock at output after
checking the LOS signal. If a LOS of presently connected signal goes high
then next priority signal should be connected at output but this
connection should be resynced only if the current connected LOS goes
high.
Can anybody suggest the proper logic for the same . Device choosen is
ALTERA's EPM3128ATC100-10.
Thanx in advance.
Anupam

 

[Neo]

You can xor the clock and not of clock for each clock and use that to
check for clock's presence then prioritise that logic to output your
reqd clock.
but I am doubtful if fpga logic allows you to do it.

 

[Pieter Hulshoff]

aaaaaa wrote:

I have 21 input clock signal and 21 correwsponding los signals . If a
clock (out of these 21) is not coming the los signal of that clock will
come as "high".
CPU can write the priority of these 21 clocks thru chip_select add and
data bus. I want to connect the highest priority clock at output after
checking the LOS signal. If a LOS of presently connected signal goes high
then next priority signal should be connected at output but this
connection should be resynced only if the current connected LOS goes
high.

I'm not quite sure what kind of help you're asking for. Is it the LOS
detection you're struggling with or the clock selection? Please, also
remember to take into consideration to
1. Possibly filter the LOS signal over a certain time.
2. Make sure when switching clocks that you're not creating glitches.
What are your requirements with regards to the switching of the clocks, and
the clock level times of the output clock?

Regards,

Pieter Hulshoff