clock and stable data

[john]

Hi,

I am serially outing the 48 bits of data at the rising edge of the
clock. My DAC needs the data to be stable before the rising edge of
the clock. How can I make the data available or stable just before the
rising edge of the clock.
if rising_edge (clk_a) then
if (count_begin = '1') then
p2s_counter<=p2s_counter
+1;
ser_out <= ser_buff ( to_integer ( p2s_counter ));
end if;
end if;

Regards,
John

 

[JK]

On Apr 25, 10:22 pm, john <conphil...@hotmail.com> wrote:

Hi,

I am serially outing the 48 bits of data at the rising edge of the
clock. My DAC needs the data to be stable before the rising edge of
the clock. How can I make the data available or stable just before the
rising edge of the clock.
if rising_edge (clk_a) then
if (count_begin = '1') then
p2s_counter<=p2s_counter
+1;
ser_out <= ser_buff ( to_integer ( p2s_counter ));
end if;
end if;

Regards,
John

If your DAC needs data with rising edge of the clock, then shift your
data at falling edge of the clock.