CLOCK AND DATA RECOVERY PROBLEM

[chetan]

HI ,
I AM WORKING IN THE AREA OF SDH AND IN THIS OPTICAL DATA DIFFERENTIAL
( STM-1 ) OF 155MBPS IS COMING IN AND I WILL CONVERT IT INTO NORMAL
DATA AND THEN I HAVE TO PASS IT THROUGH CDR TO RECOVER ACTUAL DATA AND
CLOCK.

I AM USING XILINX DATA RECOVERY VERILOG FILE ( xapp224 is pdf) for
clock and data recovery. The problem is that here i require the system
clock 155Mhz and 90 degress phase shift clock of the same. i used pll
for the generation of 155 Mhz and 90degrees phase shift clock as the
clock input to my module is 19.44 Mhz.

if i simulate this block i am getting the data recovered perfectly.
but if i model the clocks to CDR with jitter the data is not recovered
perfectly it is giving errors.
i want output to be perfect even with jitter as 3%.
Does any body have the verilog code or design doc of CDR which will
work fine at this jitter level.
Can any one suggest me the methods to design the CDR with the specs.

i am using Virtex 5 lx30t FPGA

Thank you