CLKFX problem with a Virtex II

[jean-francois hasson]

Hi,

In the design I am working on there is (for the moment) a DCM
generating a CLK0, CLK2X and CLKFX outputs with CLKIN being 40 MHz and
no reset on the RST pin of the DCM (tied to VCC). All seems fine
during functionnal simulation but on the board the CLKFX does not
toggle (STATUS<2> of DCM is high but the LOCK is high too !?!). What
is confusing among other things is that a previous version of this
design was previously working fine on the board regarding this clock
at 160 MHz (clkfx). The difference between this failing version and
the previous one that I can think of is the fact that a fair amount of
logic has been added otherwise same board, same fpga, same clocking
scheme, ... If anyone can give me a piece of advice that would be of
great help. I will do further inverstigation in the mean time.

Thanks,

JF

 

[Austin Lesea]

Jean-Francois,

Use the DCM reset. It may be that the DCM is unable to use the input
clock immediately after DONE goes high, and the DFS part of the DCM is
unable to LOCK.

This is a fairly common start up issue with many oscillators, and for that
reason we recommend connecting the reset to the local chip logic reset, or
to some other circuit that checks the LOCKED bit, the CLKFX_STOPPED bit,
and the CLKIN_STOPPED status bits so you know when the DCM has had a
hiccup (due to the external clock) and can restart it.

Austin

jean-francois hasson wrote:

Hi,

In the design I am working on there is (for the moment) a DCM
generating a CLK0, CLK2X and CLKFX outputs with CLKIN being 40 MHz and
no reset on the RST pin of the DCM (tied to VCC). All seems fine
during functionnal simulation but on the board the CLKFX does not
toggle (STATUS<2> of DCM is high but the LOCK is high too !?!). What
is confusing among other things is that a previous version of this
design was previously working fine on the board regarding this clock
at 160 MHz (clkfx). The difference between this failing version and
the previous one that I can think of is the fact that a fair amount of
logic has been added otherwise same board, same fpga, same clocking
scheme, ... If anyone can give me a piece of advice that would be of
great help. I will do further inverstigation in the mean time.

Thanks,

JF