C
Carl Ingemarsson
Guest
Hi everyone!
I've been trying to constraint a carry chain in my Virtex 4 design to
be placed so that the least significant part of it is in the upper
part of a CLB. By doing this I would have a little more "near" sites
for the lower significant input registers. I want to run ny design
fairy fast and the carry chain is critical. If it's relevant I am
using Xilinx software.
I've managed to do this with fixed location constraints from
PlanAhead, but I would want to use RLOC (and BEL) constraints in my
vhdl source instead since my component is instantiated several times.
I've only been able to use RLOC constraints for this Virtex 4 design
with XY coordinates. Is it somehow possible to have CLB relative RLOC
constraints with Virtex 4? Or is their any other nice solution to my
problem?
I've been trying to constraint a carry chain in my Virtex 4 design to
be placed so that the least significant part of it is in the upper
part of a CLB. By doing this I would have a little more "near" sites
for the lower significant input registers. I want to run ny design
fairy fast and the carry chain is critical. If it's relevant I am
using Xilinx software.
I've managed to do this with fixed location constraints from
PlanAhead, but I would want to use RLOC (and BEL) constraints in my
vhdl source instead since my component is instantiated several times.
I've only been able to use RLOC constraints for this Virtex 4 design
with XY coordinates. Is it somehow possible to have CLB relative RLOC
constraints with Virtex 4? Or is their any other nice solution to my
problem?