R
Rob Doyle
Guest
I've designed a PDP8 computer and RK08 disk drive controller.
I'm trying to test the RK08 controller with a simulated RK05
disk drive. The RK05 disk drive essentially has 6496
sectors and each sector has 256 (16 bit, 4 bits unused) words.
All disk operations occurs on sectors: a sector can be read
or written.
I have a 3,325,952 byte disk image that has the OS image
for testing.
I'm trying to write a testbench in VHDL that simulates the
RK05 disk drive using file IO. I don't do a lot of file IO
in VHDL and I'm struggling.
As far as I can see:
VHDL seems to preclude opening a file for read and write,
(or modification).
VHDL doesn't seem to have an easy way to 'seek' through
a file.
Verilog has $fseek() which seems like it would significantly
simplify everything. I'm not sure if Verilog can open
a file for read/write/update, either.
I *could* re-do the testbench in Verilog if doing this in
VHDL was impossible but:
- I'm much less competent in Verilog.
- I'd have to give up having a nice PDP8 simulator executable
generated by GHDL.
My preference would be to stick with VHDL.
Any suggestions?
Rob.
I'm trying to test the RK08 controller with a simulated RK05
disk drive. The RK05 disk drive essentially has 6496
sectors and each sector has 256 (16 bit, 4 bits unused) words.
All disk operations occurs on sectors: a sector can be read
or written.
I have a 3,325,952 byte disk image that has the OS image
for testing.
I'm trying to write a testbench in VHDL that simulates the
RK05 disk drive using file IO. I don't do a lot of file IO
in VHDL and I'm struggling.
As far as I can see:
VHDL seems to preclude opening a file for read and write,
(or modification).
VHDL doesn't seem to have an easy way to 'seek' through
a file.
Verilog has $fseek() which seems like it would significantly
simplify everything. I'm not sure if Verilog can open
a file for read/write/update, either.
I *could* re-do the testbench in Verilog if doing this in
VHDL was impossible but:
- I'm much less competent in Verilog.
- I'd have to give up having a nice PDP8 simulator executable
generated by GHDL.
My preference would be to stick with VHDL.
Any suggestions?
Rob.