U
usustarr
Guest
i have a design a trasaction base test bench and an interface. but i
need to convert same design in to a class bace test bench. Can anyone
please tell me how to do this? i will poste my files below.
==================================== testbench.sv
=======================
`include "calc2_top.sv"
module atest;
timeunit 1ns;
timeprecision 1ps;
wire scan_out;
reg a_clk, b_clk, c_clk, reset, scan_in;
wire out_adder_overflow, port1_invalid_op, port2_invalid_op,
port3_invalid_op, port4_invalid_op, prio_adder_out_vld,
prio_shift_out_vld, scan_ring1, scan_ring2, scan_ring3, scan_ring4,
scan_ring5, scan_ring6, scan_ring7, scan_ring8, scan_ring9,
scan_ring10, scan_ring11, shift_overflow;
// ============================================ interface
======================================
apb inter( );
//================================== Top level module
==============================================
// name the_bus1 came from the top level module. it was given name in
top level module.
// inter is the interface name came from interface instantiation
(above). //one is the modport name
calc2_top C2 (.the_bus1(inter.one),
.the_bus2(inter.two),
.the_bus3(inter.three),
.the_bus4(inter.four),
.*
);
initial begin
c_clk = 0;
a_clk = 0;
b_clk = 0;
scan_in = 0;
end
// ================================ The clock genarator
=====================================
always #100 c_clk = ~c_clk;
//=====================================instantiate program
====================================
cal_program program_inst(
.c_clk(c_clk),
.reset(reset),
.req1_cmd_in(inter.one.req1_cmd_in),
.req2_cmd_in(inter.two.req2_cmd_in),
.req3_cmd_in(inter.three.req3_cmd_in),
.req4_cmd_in(inter.four.req4_cmd_in),
.req1_tag_in(inter.one.req1_tag_in),
.req2_tag_in(inter.two.req2_tag_in),
.req3_tag_in(inter.three.req3_tag_in),
.req4_tag_in(inter.four.req4_tag_in),
.req1_data_in(inter.one.req1_data_in),
.req2_data_in(inter.two.req2_data_in),
.req3_data_in(inter.three.req3_data_in),
.req4_data_in(inter.four.req4_data_in),
.out_data1(inter.one.out_data1),
.out_data2(inter.two.out_data2),
.out_data3(inter.three.out_data3),
.out_data4(inter.four.out_data4),
.out_resp1(inter.one.out_resp1),
.out_resp2(inter.two.out_resp2),
.out_resp3(inter.three.out_resp3),
.out_resp4(inter.four.out_resp4),
.out_tag1(inter.one.out_tag1),
.out_tag2(inter.two.out_tag2),
.out_tag3(inter.three.out_tag3),
.out_tag4(inter.four.out_tag4)
);
endmodule
================================ calc2_top.sv
=================================
// apb is the interface module name. the_bus1 is the modport name.
the_bus1 is just a given name.
module calc2_top (apb.one the_bus1,
apb.two the_bus2,
apb.three the_bus3,
apb.four the_bus4,
output scan_out,
input reset, scan_in, a_clk, b_clk, c_clk);
wire out_adder_overflow, port1_invalid_op, port2_invalid_op,
port3_invalid_op, port4_invalid_op, prio_adder_out_vld,
prio_shift_out_vld, scan_ring1, scan_ring2, scan_ring3, scan_ring4,
scan_ring5, scan_ring6, scan_ring7, scan_ring8, scan_ring9,
scan_ring10, scan_ring11, shift_overflow;
wire [0:31] addmux_out_data1, addmux_out_data2, addmux_out_data3,
addmux_out_data4 , hold1_prio_data1, hold1_prio_data2,
hold2_prio_data1, hold2_prio_data2 , hold3_prio_data1,
hold3_prio_data2, hold4_prio_data1, hold4_prio_data2;
wire [0:1] addmux_out_resp1, addmux_out_resp2, addmux_out_resp3,
addmux_out_resp4, addmux_out_tag1, addmux_out_tag2, addmux_out_tag3,
addmux_out_tag4, hold1_prio_tag,hold2_prio_tag , hold3_prio_tag,
hold4_prio_tag;
wire [0:3] hold1_prio_cmd, hold2_prio_cmd,hold3_prio_cmd,
hold4_prio_cmd;
wire [0:3] instage_adder_cmd, instage_shift_cmd;
wire [0:63] instage_adder_data1, instage_adder_data2,
instage_shift_data1, instage_shift_data2, out_adder_data,
shift_out_data;
wire [0:1] port1_invalid_tag, port2_invalid_tag,
port3_invalid_tag, port4_invalid_tag;
wire [0:3] prio_adder_cmd, prio_adder_tag, prio_shift_cmd,
prio_shift_tag;
wire [0:31] prio_adder_data1, prio_adder_data2, prio_shift_data1,
prio_shift_data2;
wire [0:31] shiftmux_out_data1, shiftmux_out_data2,
shiftmux_out_data3, shiftmux_out_data4;
wire [0:1] shiftmux_out_resp1, shiftmux_out_resp2,
shiftmux_out_resp3,shiftmux_out_resp4, shiftmux_out_tag1,
shiftmux_out_tag2, shiftmux_out_tag3, shiftmux_out_tag4;
adder adder1(
.alu_cmd(instage_adder_cmd),
.bin_ovfl(out_adder_overflow),
.bin_sum(out_adder_data[0:63]),
.fxu_areg_q(instage_adder_data1) ,
.fxu_breg_q(instage_adder_data2) );
alu_input_stage adder_input(
.alu_cmd(instage_adder_cmd),
.alu_data1(instage_adder_data1),
.alu_data2(instage_adder_data2) ,
.prio_cmd(prio_adder_cmd) ,
.prio_data1(prio_adder_data1),
.prio_data2(prio_adder_data2) );
alu_output_stage adder_output_stage(
.a_clk(a_clk),
.alu_overflow(out_adder_overflow),
.alu_result(out_adder_data),
.b_clk(b_clk),
.c_clk(c_clk),
.out_data1(addmux_out_data1),
.out_data2(addmux_out_data2),
.out_data3(addmux_out_data3),
.out_data4(addmux_out_data4),
.out_resp1(addmux_out_resp1),
.out_resp2(addmux_out_resp2),
.out_resp3(addmux_out_resp3),
.out_resp4(addmux_out_resp4),
.out_tag1(addmux_out_tag1),
.out_tag2(addmux_out_tag2),
.out_tag3(addmux_out_tag3),
.out_tag4(addmux_out_tag4),
.prio_alu_out_vld(prio_adder_out_vld),
.prio_alu_tag (prio_adder_tag),
.reset(reset),
.scan_in(scan_ring5),
.scan_out(scan_ring6) );
holdreg holdreg1(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold1_prio_data1),
.hold_data2(hold1_prio_data2),
.hold_prio_req(hold1_prio_cmd),
.hold_prio_tag(hold1_prio_tag),
.req_cmd_in(the_bus1.req1_cmd_in), // modified
.req_data_in(the_bus1.req1_data_in), // modified
.req_tag_in(the_bus1.req1_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
holdreg holdreg2(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold2_prio_data1),
.hold_data2(hold2_prio_data2),
.hold_prio_req(hold2_prio_cmd),
.hold_prio_tag(hold2_prio_tag),
.req_cmd_in(the_bus2.req2_cmd_in), // modified
.req_data_in(the_bus2.req2_data_in), // modified
.req_tag_in(the_bus2.req2_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
holdreg holdreg3(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold3_prio_data1),
.hold_data2(hold3_prio_data2),
.hold_prio_req(hold3_prio_cmd),
.hold_prio_tag(hold3_prio_tag),
.req_cmd_in(the_bus3.req3_cmd_in), // modified
.req_data_in(the_bus3.req3_data_in), // modified
.req_tag_in(the_bus3.req3_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
holdreg holdreg4(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold4_prio_data1),
.hold_data2(hold4_prio_data2),
.hold_prio_req(hold4_prio_cmd),
.hold_prio_tag(hold4_prio_tag),
.req_cmd_in(the_bus4.req4_cmd_in), // modified
.req_data_in(the_bus4.req4_data_in), // modified
.req_tag_in(the_bus4.req4_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
mux_out mux_out4(
.a_clk(a_clk),
.adder_data(addmux_out_data4),
.adder_resp(addmux_out_resp4),
.adder_tag(addmux_out_tag4),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port4_invalid_op),
.invalid_op_tag(port4_invalid_tag),
.req_data(the_bus4.out_data4), // modified
.req_resp(the_bus4.out_resp4), // modified
.req_tag(the_bus4.out_tag4), // modified
.reset(reset),
.scan_in(scan_ring11),
.scan_out(scan_out),
.shift_data(shiftmux_out_data4),
.shift_resp(shiftmux_out_resp4),
.shift_tag(shiftmux_out_tag4) );
mux_out mux_out3(
.a_clk(a_clk),
.adder_data(addmux_out_data3),
.adder_resp(addmux_out_resp3),
.adder_tag(addmux_out_tag3),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port3_invalid_op),
.invalid_op_tag(port3_invalid_tag),
.req_data(the_bus3.out_data3),
.req_resp(the_bus3.out_resp3),
.req_tag(the_bus3.out_tag3),
.reset(reset),
.scan_in(scan_ring10),
.scan_out(scan_ring11),
.shift_data(shiftmux_out_data3),
.shift_resp(shiftmux_out_resp3),
.shift_tag(shiftmux_out_tag3) );
mux_out mux_out2(
.a_clk(a_clk),
.adder_data(addmux_out_data2),
.adder_resp(addmux_out_resp2),
.adder_tag(addmux_out_tag2),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port2_invalid_op),
.invalid_op_tag(port2_invalid_tag),
.req_data(the_bus2.out_data2), // modified
.req_resp(the_bus2.out_resp2), // modified
.req_tag(the_bus2.out_tag2), // modified
.reset(reset),
.scan_in(scan_ring9),
.scan_out(scan_ring10),
.shift_data(shiftmux_out_data2),
.shift_resp(shiftmux_out_resp2),
.shift_tag(shiftmux_out_tag2) );
mux_out mux_out1(.
a_clk(a_clk),
.adder_data(addmux_out_data1),
.adder_resp(addmux_out_resp1),
.adder_tag(addmux_out_tag1),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port1_invalid_op),
.invalid_op_tag(port1_invalid_tag),
.req_data(the_bus1.out_data1), // modified
.req_resp(the_bus1.out_resp1), // modified
.req_tag(the_bus1.out_tag1), // modified
.reset(reset),
.scan_in(scan_ring8),
.scan_out(scan_ring9),
.shift_data(shiftmux_out_data1),
.shift_resp(shiftmux_out_resp1),
.shift_tag(shiftmux_out_tag1) );
priority_one priority1(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold1_cmd(hold1_prio_cmd),
.hold1_data1( hold1_prio_data1),
.hold1_data2(hold1_prio_data2),
.hold1_tag(hold1_prio_tag),
.hold2_cmd(hold2_prio_cmd),
.hold2_data1(hold2_prio_data1),
.hold2_data2(hold2_prio_data2),
.hold2_tag(hold2_prio_tag),
.hold3_cmd(hold3_prio_cmd),
.hold3_data1(hold3_prio_data1),
.hold3_data2(hold3_prio_data2),
.hold3_tag(hold3_prio_tag),
.hold4_cmd(hold4_prio_cmd),
.hold4_data1(hold4_prio_data1),
.hold4_data2(hold4_prio_data2),
.hold4_tag(hold4_prio_tag),
.port1_invalid_op(port1_invalid_op),
.port1_invalid_tag(port1_invalid_tag),
.port2_invalid_op(port2_invalid_op),
.port2_invalid_tag(port2_invalid_tag),
.port3_invalid_op(port3_invalid_op),
.port3_invalid_tag(port3_invalid_tag),
.port4_invalid_op(port4_invalid_op),
.port4_invalid_tag(port4_invalid_tag),
.prio_adder_cmd(prio_adder_cmd),
.prio_adder_data1(prio_adder_data1),
.prio_adder_data2(prio_adder_data2),
.prio_adder_out_vld(prio_adder_out_vld),
.prio_adder_tag(prio_adder_tag),
.prio_shift_cmd(prio_shift_cmd),
.prio_shift_data1(prio_shift_data1),
.prio_shift_data2(prio_shift_data2),
.prio_shift_out_vld(prio_shift_out_vld),
.prio_shift_tag(prio_shift_tag),
.reset(reset),
.scan_in(scan_ring4),
.scan_out(scan_ring5) );
shifter shifter1(
.a_clk (a_clk) ,
.b_clk(b_clk),
.c_clk(c_clk),
.bin_ovfl(bin_ovfl),
.shift_out(shift_out_data),
.shift_cmd(instage_shift_cmd),
.shift_places(instage_shift_data2),
.shift_val(instage_shift_data1),
.reset(reset),
.scan_in(scan_ring6),
.scan_out(scan_ring7) );
alu_input_stage shifter_input (
.alu_cmd(instage_shift_cmd),
.alu_data1(instage_shift_data1),
.alu_data2(instage_shift_data2),
.prio_cmd(prio_shift_cmd),
.prio_data1(prio_shift_data1),
.prio_data2(prio_shift_data2) );
alu_output_stage shifter_output_stage (
.a_clk (a_clk),
.alu_overflow ( shift_overflow),
.alu_result ( shift_out_data),
.b_clk ( b_clk),
.c_clk ( c_clk),
.out_data1( shiftmux_out_data1),
.out_data2(shiftmux_out_data2),
.out_data3(shiftmux_out_data3),
.out_data4 (shiftmux_out_data4),
.out_resp1 (shiftmux_out_resp1),
.out_resp2(shiftmux_out_resp2),
.out_resp3 ( shiftmux_out_resp3),
.out_resp4 ( shiftmux_out_resp4),
.out_tag1 ( shiftmux_out_tag1),
.out_tag2 ( shiftmux_out_tag2),
.out_tag3 ( shiftmux_out_tag3),
.out_tag4 ( shiftmux_out_tag4),
.prio_alu_out_vld ( prio_shift_out_vld),
.prio_alu_tag ( prio_shift_tag),
.reset ( reset),
.scan_in ( scan_ring7),
.scan_out ( scan_ring8) );
// ===== instantiation for assertions ================
assertion assertion_inst(
.out_resp1(the_bus1.out_resp1),
.out_resp2(the_bus2.out_resp2),
.out_resp3(the_bus3.out_resp3),
.out_resp4(the_bus4.out_resp4),
.c_clk(c_clk),
.req1_cmd_in(the_bus1.req1_cmd_in),
.req2_cmd_in(the_bus2.req2_cmd_in),
.req3_cmd_in(the_bus3.req3_cmd_in),
.req4_cmd_in(the_bus4.req4_cmd_in),
.req1_data_in(the_bus1.req1_data_in),
.req2_data_in(the_bus2.req2_data_in),
.req3_data_in(the_bus3.req3_data_in),
.req4_data_in(the_bus4.req4_data_in),
.out_data1(the_bus1.out_data1),
.out_data2(the_bus2.out_data2),
.out_data3(the_bus3.out_data3),
.out_data4(the_bus4.out_data4)
);
endmodule
========================cal_program.sv ==========================
program cal_program(
input logic c_clk,
output logic reset,
output logic[0:3] req1_cmd_in, req2_cmd_in, req3_cmd_in,
req4_cmd_in,
output logic[0:1] req1_tag_in, req2_tag_in, req3_tag_in,
req4_tag_in,
output logic[0:31] req1_data_in, req2_data_in, req3_data_in,
req4_data_in,
input logic[0:31] out_data1, out_data2, out_data3, out_data4,
input logic[0:1] out_resp1, out_resp2, out_resp3, out_resp4,
out_tag1, out_tag2, out_tag3, out_tag4
);
timeunit 1ns;
timeprecision 1ps;
import cal_package::*;
//clocking block
clocking cb @(negedge c_clk);
default input #1step output #1ns;
input out_data1, out_data2, out_data3, out_data4;
input out_resp1, out_resp2, out_resp3, out_resp4, out_tag1,
out_tag2, out_tag3, out_tag4;
output reset;
output req1_cmd_in, req2_cmd_in, req3_cmd_in, req4_cmd_in;
output req1_tag_in, req2_tag_in, req3_tag_in, req4_tag_in;
output req1_data_in, req2_data_in, req3_data_in, req4_data_in;
endclocking
initial begin
reset <= 1;
req1_cmd_in <= 0;
req1_data_in <= 0 ;
req1_tag_in <= 0;
req2_cmd_in <= 0;
req2_data_in <= 0;
req2_tag_in <= 0;
req3_cmd_in <= 0;
req3_data_in <= 0;
req3_tag_in <= 0;
req4_cmd_in <= 0;
req4_data_in <= 0;
req4_tag_in <= 0;
#600 //ADD command
cb.reset <= 0;
build_P1_cmd(4'b1,2'b1,32'd10);
build_P2_cmd(4'b1,2'b1,32'd100000);
build_P3_cmd(4'b1,2'b1,{{30{1'b1}}, 1'b0});
build_P4_cmd(4'b1,2'b1,{{20{1'b1}}, 1'b0});
#200 //800ns
build_P1_cmd(4'b0,2'b0,32'd25);
build_P2_cmd(4'b0,2'b0,32'd200000);
build_P3_cmd(4'b0,2'b0,32'd2);
build_P4_cmd(4'b0,2'b0,32'd5);
#200 //SUB command 1000ns
build_P1_cmd(4'd2,2'd2,32'd5);
build_P2_cmd(4'd2,2'd2,32'd10);
build_P3_cmd(4'd2,2'd2,32'd50000);
build_P4_cmd(4'd2,2'd2,{31{1'b1}});
#200 //1200ns
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
#200//ADD command 1400ns
build_P1_cmd(4'b1,2'd3,32'b111110000011111000001111100000);
build_P2_cmd(4'b1,2'd3,32'b1011);
build_P3_cmd(4'b1,2'd3,32'b111100011);
build_P4_cmd(4'b1,2'd3,32'b100000000001);
add_checker(32'd10,32'd25,out_data1); //out_data1 should be 35
#200 //1600ns
build_P1_cmd(4'b0,2'b0,32'b000001111100000111110000011111);
build_P2_cmd(4'b0,2'b0,32'b1001);
build_P3_cmd(4'b0,2'b0,32'b11100011);
build_P4_cmd(4'b0,2'b0,32'b10);
add_checker(32'd100000,32'd200000,out_data2);//out_data2 should be
3000000
sub_checker(32'd5,32'd5,out_data1); //out_data1 should be 0
#200 //ADD 1800ns
build_P1_cmd(4'b1,2'b0,32'b100);
build_P2_cmd(4'b1,2'b0,32'b1000);
build_P3_cmd(4'b1,2'b0,32'b10000);
build_P4_cmd(4'b1,2'b0,32'b100000);
add_checker({{30{1'b1}}, 1'b0},32'd2,out_data3);
#200 //2000ns
build_P1_cmd(4'b0,2'b0,32'b100);
build_P2_cmd(4'b0,2'b0,32'b1000);
build_P3_cmd(4'b0,2'b0,32'b10000);
build_P4_cmd(4'b0,2'b0,32'b100000);
add_checker({{20{1'b1}}, 1'b0},32'd5,out_data4);
#200//SUB 2200ns
build_P1_cmd(4'd2,2'b1,32'd5);
build_P2_cmd(4'd2,2'b1,32'd10);
build_P3_cmd(4'd2,2'b1,32'd50000);
build_P4_cmd(4'd2,2'b1,{31{1'b1}});
sub_checker({31{1'b1}},{31{1'b1}},out_data4);
#200 //2400ns
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
sub_checker(32'd10,32'd9,out_data2);
#200 //ADD 2600ns
build_P1_cmd(4'b1,2'd2,32'd5);
build_P2_cmd(4'b1,2'd2,32'd10);
build_P3_cmd(4'b1,2'd2,32'd50000);
build_P4_cmd(4'b1,2'd2,{31{1'b1}});
sub_checker(32'd50000,32'd1999,out_data3);
#200
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
#200 //SHIFT LEFT
build_P1_cmd(4'd5,2'd3,32'b1111);
build_P2_cmd(4'd5,2'd3,32'b1010101);
build_P3_cmd(4'd5,2'd3,{{30{1'b1}}, 1'b0});
build_P4_cmd(4'd5,2'd3,{{20{1'b1}}, 1'b0});
#200
build_P1_cmd(4'b0,2'b0,32'd2);
build_P2_cmd(4'b0,2'b0,32'd5);
build_P3_cmd(4'b0,2'b0,32'd20);
build_P4_cmd(4'b0,2'b0,32'd32);
#200 //ADD
build_P1_cmd(4'b1,2'd2,32'd5);
build_P2_cmd(4'b1,2'd2,32'd10);
build_P3_cmd(4'b1,2'd2,32'd50000);
build_P4_cmd(4'b1,2'd2,{31{1'b1}});
#200
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
#200 //SHIFT RIGHT
build_P1_cmd(4'd6,2'b0,{31{1'b1}});
build_P2_cmd(4'd6,2'b0,32'b111100001111);
build_P3_cmd(4'd6,2'b0,32'b101010);
build_P4_cmd(4'd6,2'b0,{15{1'b1}});
#200
build_P1_cmd(4'b0,2'b0,32'd2);
build_P2_cmd(4'b0,2'b0,32'd4);
build_P3_cmd(4'b0,2'b0,32'd20);
build_P4_cmd(4'b0,2'b0,32'd32);
shl_checker(32'b1111,32'd2,out_data1);
#200 //shift left
build_P1_cmd(4'd5,2'b1,32'b1011011101111);
build_P2_cmd(4'd5,2'b1,32'b1111110000011);
build_P3_cmd(4'd5,2'b1,32'b1010011100100);
build_P4_cmd(4'd5,2'b1,32'b100101010101);
shl_checker(32'b1010101,32'd4,out_data2);
#200
build_P1_cmd(4'b0,2'b0,32'd2);
build_P2_cmd(4'b0,2'b0,32'd5);
build_P3_cmd(4'b0,2'b0,32'd15);
build_P4_cmd(4'b0,2'b0,32'd20);
shl_checker({30{1'b1}},32'd20,out_data3);
#200 //shift right
build_P1_cmd(4'd6,2'd2,{31{1'b1}});
build_P2_cmd(4'd6,2'd2,{25{1'b1}});
build_P3_cmd(4'd6,2'd2,{ {10{1'b1}},{10{1'b0}},{10{1'b1}} });
build_P4_cmd(4'd6,2'd2,{5{1'b1}});
shl_checker({{20{1'b1}}, 1'b0},32'd32,out_data4);
#200
build_P1_cmd(4'b0,2'b0,32'd10);
build_P2_cmd(4'b0,2'b0,32'd20);
build_P3_cmd(4'b0,2'b0,32'd29);
build_P4_cmd(4'b0,2'b0,32'd3);
#600
shr_checker({31{1'b1}},32'd10,out_data1);
#200
shr_checker({25{1'b1}},32'd20,out_data2);
#200
shr_checker({{10{1'b1}},{10{1'b0}},{10{1'b1}}},32'd29,out_data3);
#200
shr_checker({5{1'b1}},32'd3,out_data4);
#2000 $stop;
end
// initial begin
// ====================================== checker
===================================//
task add_checker(input[31:0]operand1,operand2,sum);
begin
reg[31:0] expected;
logic[15:0] add_error_num=0;
expected = operand1+operand2;
if(expected!==sum)
begin
$display("add error",$time);
add_error_num++;
$display("ADD error numbers are", add_error_num);
end
end
endtask
task sub_checker(input[31:0]operand1,operand2,sub);
begin
reg[31:0] expected;
logic[15:0] sub_error_num=0;
expected = operand1-operand2;
if(expected!==sub)
begin
$display("sub error",$time);
sub_error_num++;
$display("SUBTRACT error numbers are", sub_error_num);
end
end
endtask
//
task shl_checker(input[31:0]operand1,operand2,shl);
begin
reg[31:0] expected;
logic[15:0] shl_error_num=0;
expected = operand1 << operand2;
if(expected!==shl)
begin
$display("shift left error",$time);
shl_error_num++;
$display("SHIFT_LEFT error numbers are", shl_error_num);
end
end
endtask
task shr_checker(input[31:0]operand1,operand2,shr);
begin
reg[31:0] expected;
logic[15:0] shr_error_num=0;
expected = operand1 >> operand2;
if(expected!==shr)
begin
$display("shift right error",$time);
shr_error_num++;
$display("SHIFT_RIGHT error numbers are", shr_error_num);
end
end
endtask
//====================== function to generate expected
results ===============//
function [32:0] gen_expected_result;
input [3:0] cmd;
input [0:31] op1, op2;
case(cmd)
ADD:gen_expected_result= op1 + op2;
SUBTRACT:gen_expected_result= op1 - op2;
SHIFT_LEFT: gen_expected_result= op1<<op2;
SHIFT_RIGHT: gen_expected_result= op1>>op2;
default: gen_expected_result= 32'b0;
endcase
endfunction
//========================= build valid command
task build_P1_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req1_cmd_in <= cmd;
cb.req1_data_in <= operand;
cb.req1_tag_in <= tag;
endtask
task build_P2_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req2_cmd_in <= cmd;
cb.req2_data_in <= operand;
cb.req2_tag_in <= tag;
endtask
task build_P3_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req3_cmd_in <= cmd;
cb.req3_data_in <= operand;
cb.req3_tag_in <= tag;
endtask
task build_P4_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req4_cmd_in <= cmd;
cb.req4_data_in <= operand;
cb.req4_tag_in <= tag;
endtask
endprogram
======================cal_package.sv====================
package cal_package;
typedef enum {
ADD,
SUBTRACT,
SHIFT_RIGHT,
SHIFT_LEFT,
INVALID
} cmd;
// structs for building valid command
//
typedef struct {
int add_max;
int add_ofl1;
int add_rand;
int sub_equ;
int sub_ufl1;
int sub_rand;
int shl_min;
int shl_max;
int shl_rand;
int shr_min;
int shr_max;
int shr_rand;
} cmd_type;
endpackage
==========================APB_intf.sv
interface apb();
logic[0:3] req1_cmd_in,req2_cmd_in,req3_cmd_in,req4_cmd_in;
logic[0:31] req1_data_in,req2_data_in,req3_data_in,req4_data_in;
logic[0:1] req1_tag_in,req2_tag_in,req3_tag_in,req4_tag_in;
logic[0:1] out_resp1,out_resp2,out_resp3,out_resp4;
logic[0:31] out_data1,out_data2,out_data3,out_data4;
logic[0:1] out_tag1,out_tag2,out_tag3,out_tag4;
//--------------------------------- Mod ports
---------------------------------------//
// These go to DUT
modport one (output out_resp1, out_data1, out_tag1,
input req1_cmd_in, req1_data_in, req1_tag_in);
modport two (output out_resp2, out_data2, out_tag2,
input req2_cmd_in, req2_data_in, req2_tag_in);
modport three (output out_resp3, out_data3, out_tag3,
input req3_cmd_in, req3_data_in, req3_tag_in);
modport four (output out_resp4, out_data4, out_tag4,
input req4_cmd_in, req4_data_in, req4_tag_in);
// This comes from test bench
modport tb (output req1_cmd_in, req1_data_in, req1_tag_in,
req2_cmd_in, req2_data_in, req2_tag_in,
req3_cmd_in, req3_data_in, req3_tag_in,
req4_cmd_in, req4_data_in, req4_tag_in,
input out_resp1, out_data1, out_tag1,
out_resp2, out_data2, out_tag2,
out_resp3, out_data3, out_tag3,
out_resp4, out_data4, out_tag4
);
// inputs (outputs from DUT) to the Test bench and outputs (inputs to
the DUT)from Test bench.
endinterface:apb
=========================================
need to convert same design in to a class bace test bench. Can anyone
please tell me how to do this? i will poste my files below.
==================================== testbench.sv
=======================
`include "calc2_top.sv"
module atest;
timeunit 1ns;
timeprecision 1ps;
wire scan_out;
reg a_clk, b_clk, c_clk, reset, scan_in;
wire out_adder_overflow, port1_invalid_op, port2_invalid_op,
port3_invalid_op, port4_invalid_op, prio_adder_out_vld,
prio_shift_out_vld, scan_ring1, scan_ring2, scan_ring3, scan_ring4,
scan_ring5, scan_ring6, scan_ring7, scan_ring8, scan_ring9,
scan_ring10, scan_ring11, shift_overflow;
// ============================================ interface
======================================
apb inter( );
//================================== Top level module
==============================================
// name the_bus1 came from the top level module. it was given name in
top level module.
// inter is the interface name came from interface instantiation
(above). //one is the modport name
calc2_top C2 (.the_bus1(inter.one),
.the_bus2(inter.two),
.the_bus3(inter.three),
.the_bus4(inter.four),
.*
);
initial begin
c_clk = 0;
a_clk = 0;
b_clk = 0;
scan_in = 0;
end
// ================================ The clock genarator
=====================================
always #100 c_clk = ~c_clk;
//=====================================instantiate program
====================================
cal_program program_inst(
.c_clk(c_clk),
.reset(reset),
.req1_cmd_in(inter.one.req1_cmd_in),
.req2_cmd_in(inter.two.req2_cmd_in),
.req3_cmd_in(inter.three.req3_cmd_in),
.req4_cmd_in(inter.four.req4_cmd_in),
.req1_tag_in(inter.one.req1_tag_in),
.req2_tag_in(inter.two.req2_tag_in),
.req3_tag_in(inter.three.req3_tag_in),
.req4_tag_in(inter.four.req4_tag_in),
.req1_data_in(inter.one.req1_data_in),
.req2_data_in(inter.two.req2_data_in),
.req3_data_in(inter.three.req3_data_in),
.req4_data_in(inter.four.req4_data_in),
.out_data1(inter.one.out_data1),
.out_data2(inter.two.out_data2),
.out_data3(inter.three.out_data3),
.out_data4(inter.four.out_data4),
.out_resp1(inter.one.out_resp1),
.out_resp2(inter.two.out_resp2),
.out_resp3(inter.three.out_resp3),
.out_resp4(inter.four.out_resp4),
.out_tag1(inter.one.out_tag1),
.out_tag2(inter.two.out_tag2),
.out_tag3(inter.three.out_tag3),
.out_tag4(inter.four.out_tag4)
);
endmodule
================================ calc2_top.sv
=================================
// apb is the interface module name. the_bus1 is the modport name.
the_bus1 is just a given name.
module calc2_top (apb.one the_bus1,
apb.two the_bus2,
apb.three the_bus3,
apb.four the_bus4,
output scan_out,
input reset, scan_in, a_clk, b_clk, c_clk);
wire out_adder_overflow, port1_invalid_op, port2_invalid_op,
port3_invalid_op, port4_invalid_op, prio_adder_out_vld,
prio_shift_out_vld, scan_ring1, scan_ring2, scan_ring3, scan_ring4,
scan_ring5, scan_ring6, scan_ring7, scan_ring8, scan_ring9,
scan_ring10, scan_ring11, shift_overflow;
wire [0:31] addmux_out_data1, addmux_out_data2, addmux_out_data3,
addmux_out_data4 , hold1_prio_data1, hold1_prio_data2,
hold2_prio_data1, hold2_prio_data2 , hold3_prio_data1,
hold3_prio_data2, hold4_prio_data1, hold4_prio_data2;
wire [0:1] addmux_out_resp1, addmux_out_resp2, addmux_out_resp3,
addmux_out_resp4, addmux_out_tag1, addmux_out_tag2, addmux_out_tag3,
addmux_out_tag4, hold1_prio_tag,hold2_prio_tag , hold3_prio_tag,
hold4_prio_tag;
wire [0:3] hold1_prio_cmd, hold2_prio_cmd,hold3_prio_cmd,
hold4_prio_cmd;
wire [0:3] instage_adder_cmd, instage_shift_cmd;
wire [0:63] instage_adder_data1, instage_adder_data2,
instage_shift_data1, instage_shift_data2, out_adder_data,
shift_out_data;
wire [0:1] port1_invalid_tag, port2_invalid_tag,
port3_invalid_tag, port4_invalid_tag;
wire [0:3] prio_adder_cmd, prio_adder_tag, prio_shift_cmd,
prio_shift_tag;
wire [0:31] prio_adder_data1, prio_adder_data2, prio_shift_data1,
prio_shift_data2;
wire [0:31] shiftmux_out_data1, shiftmux_out_data2,
shiftmux_out_data3, shiftmux_out_data4;
wire [0:1] shiftmux_out_resp1, shiftmux_out_resp2,
shiftmux_out_resp3,shiftmux_out_resp4, shiftmux_out_tag1,
shiftmux_out_tag2, shiftmux_out_tag3, shiftmux_out_tag4;
adder adder1(
.alu_cmd(instage_adder_cmd),
.bin_ovfl(out_adder_overflow),
.bin_sum(out_adder_data[0:63]),
.fxu_areg_q(instage_adder_data1) ,
.fxu_breg_q(instage_adder_data2) );
alu_input_stage adder_input(
.alu_cmd(instage_adder_cmd),
.alu_data1(instage_adder_data1),
.alu_data2(instage_adder_data2) ,
.prio_cmd(prio_adder_cmd) ,
.prio_data1(prio_adder_data1),
.prio_data2(prio_adder_data2) );
alu_output_stage adder_output_stage(
.a_clk(a_clk),
.alu_overflow(out_adder_overflow),
.alu_result(out_adder_data),
.b_clk(b_clk),
.c_clk(c_clk),
.out_data1(addmux_out_data1),
.out_data2(addmux_out_data2),
.out_data3(addmux_out_data3),
.out_data4(addmux_out_data4),
.out_resp1(addmux_out_resp1),
.out_resp2(addmux_out_resp2),
.out_resp3(addmux_out_resp3),
.out_resp4(addmux_out_resp4),
.out_tag1(addmux_out_tag1),
.out_tag2(addmux_out_tag2),
.out_tag3(addmux_out_tag3),
.out_tag4(addmux_out_tag4),
.prio_alu_out_vld(prio_adder_out_vld),
.prio_alu_tag (prio_adder_tag),
.reset(reset),
.scan_in(scan_ring5),
.scan_out(scan_ring6) );
holdreg holdreg1(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold1_prio_data1),
.hold_data2(hold1_prio_data2),
.hold_prio_req(hold1_prio_cmd),
.hold_prio_tag(hold1_prio_tag),
.req_cmd_in(the_bus1.req1_cmd_in), // modified
.req_data_in(the_bus1.req1_data_in), // modified
.req_tag_in(the_bus1.req1_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
holdreg holdreg2(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold2_prio_data1),
.hold_data2(hold2_prio_data2),
.hold_prio_req(hold2_prio_cmd),
.hold_prio_tag(hold2_prio_tag),
.req_cmd_in(the_bus2.req2_cmd_in), // modified
.req_data_in(the_bus2.req2_data_in), // modified
.req_tag_in(the_bus2.req2_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
holdreg holdreg3(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold3_prio_data1),
.hold_data2(hold3_prio_data2),
.hold_prio_req(hold3_prio_cmd),
.hold_prio_tag(hold3_prio_tag),
.req_cmd_in(the_bus3.req3_cmd_in), // modified
.req_data_in(the_bus3.req3_data_in), // modified
.req_tag_in(the_bus3.req3_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
holdreg holdreg4(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold_data1(hold4_prio_data1),
.hold_data2(hold4_prio_data2),
.hold_prio_req(hold4_prio_cmd),
.hold_prio_tag(hold4_prio_tag),
.req_cmd_in(the_bus4.req4_cmd_in), // modified
.req_data_in(the_bus4.req4_data_in), // modified
.req_tag_in(the_bus4.req4_tag_in), // modified
.reset(reset),
.scan_in(scan_in),
.scan_out(scan_ring1) );
mux_out mux_out4(
.a_clk(a_clk),
.adder_data(addmux_out_data4),
.adder_resp(addmux_out_resp4),
.adder_tag(addmux_out_tag4),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port4_invalid_op),
.invalid_op_tag(port4_invalid_tag),
.req_data(the_bus4.out_data4), // modified
.req_resp(the_bus4.out_resp4), // modified
.req_tag(the_bus4.out_tag4), // modified
.reset(reset),
.scan_in(scan_ring11),
.scan_out(scan_out),
.shift_data(shiftmux_out_data4),
.shift_resp(shiftmux_out_resp4),
.shift_tag(shiftmux_out_tag4) );
mux_out mux_out3(
.a_clk(a_clk),
.adder_data(addmux_out_data3),
.adder_resp(addmux_out_resp3),
.adder_tag(addmux_out_tag3),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port3_invalid_op),
.invalid_op_tag(port3_invalid_tag),
.req_data(the_bus3.out_data3),
.req_resp(the_bus3.out_resp3),
.req_tag(the_bus3.out_tag3),
.reset(reset),
.scan_in(scan_ring10),
.scan_out(scan_ring11),
.shift_data(shiftmux_out_data3),
.shift_resp(shiftmux_out_resp3),
.shift_tag(shiftmux_out_tag3) );
mux_out mux_out2(
.a_clk(a_clk),
.adder_data(addmux_out_data2),
.adder_resp(addmux_out_resp2),
.adder_tag(addmux_out_tag2),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port2_invalid_op),
.invalid_op_tag(port2_invalid_tag),
.req_data(the_bus2.out_data2), // modified
.req_resp(the_bus2.out_resp2), // modified
.req_tag(the_bus2.out_tag2), // modified
.reset(reset),
.scan_in(scan_ring9),
.scan_out(scan_ring10),
.shift_data(shiftmux_out_data2),
.shift_resp(shiftmux_out_resp2),
.shift_tag(shiftmux_out_tag2) );
mux_out mux_out1(.
a_clk(a_clk),
.adder_data(addmux_out_data1),
.adder_resp(addmux_out_resp1),
.adder_tag(addmux_out_tag1),
.b_clk(b_clk),
.c_clk(c_clk),
.invalid_op(port1_invalid_op),
.invalid_op_tag(port1_invalid_tag),
.req_data(the_bus1.out_data1), // modified
.req_resp(the_bus1.out_resp1), // modified
.req_tag(the_bus1.out_tag1), // modified
.reset(reset),
.scan_in(scan_ring8),
.scan_out(scan_ring9),
.shift_data(shiftmux_out_data1),
.shift_resp(shiftmux_out_resp1),
.shift_tag(shiftmux_out_tag1) );
priority_one priority1(
.a_clk(a_clk),
.b_clk(b_clk),
.c_clk(c_clk),
.hold1_cmd(hold1_prio_cmd),
.hold1_data1( hold1_prio_data1),
.hold1_data2(hold1_prio_data2),
.hold1_tag(hold1_prio_tag),
.hold2_cmd(hold2_prio_cmd),
.hold2_data1(hold2_prio_data1),
.hold2_data2(hold2_prio_data2),
.hold2_tag(hold2_prio_tag),
.hold3_cmd(hold3_prio_cmd),
.hold3_data1(hold3_prio_data1),
.hold3_data2(hold3_prio_data2),
.hold3_tag(hold3_prio_tag),
.hold4_cmd(hold4_prio_cmd),
.hold4_data1(hold4_prio_data1),
.hold4_data2(hold4_prio_data2),
.hold4_tag(hold4_prio_tag),
.port1_invalid_op(port1_invalid_op),
.port1_invalid_tag(port1_invalid_tag),
.port2_invalid_op(port2_invalid_op),
.port2_invalid_tag(port2_invalid_tag),
.port3_invalid_op(port3_invalid_op),
.port3_invalid_tag(port3_invalid_tag),
.port4_invalid_op(port4_invalid_op),
.port4_invalid_tag(port4_invalid_tag),
.prio_adder_cmd(prio_adder_cmd),
.prio_adder_data1(prio_adder_data1),
.prio_adder_data2(prio_adder_data2),
.prio_adder_out_vld(prio_adder_out_vld),
.prio_adder_tag(prio_adder_tag),
.prio_shift_cmd(prio_shift_cmd),
.prio_shift_data1(prio_shift_data1),
.prio_shift_data2(prio_shift_data2),
.prio_shift_out_vld(prio_shift_out_vld),
.prio_shift_tag(prio_shift_tag),
.reset(reset),
.scan_in(scan_ring4),
.scan_out(scan_ring5) );
shifter shifter1(
.a_clk (a_clk) ,
.b_clk(b_clk),
.c_clk(c_clk),
.bin_ovfl(bin_ovfl),
.shift_out(shift_out_data),
.shift_cmd(instage_shift_cmd),
.shift_places(instage_shift_data2),
.shift_val(instage_shift_data1),
.reset(reset),
.scan_in(scan_ring6),
.scan_out(scan_ring7) );
alu_input_stage shifter_input (
.alu_cmd(instage_shift_cmd),
.alu_data1(instage_shift_data1),
.alu_data2(instage_shift_data2),
.prio_cmd(prio_shift_cmd),
.prio_data1(prio_shift_data1),
.prio_data2(prio_shift_data2) );
alu_output_stage shifter_output_stage (
.a_clk (a_clk),
.alu_overflow ( shift_overflow),
.alu_result ( shift_out_data),
.b_clk ( b_clk),
.c_clk ( c_clk),
.out_data1( shiftmux_out_data1),
.out_data2(shiftmux_out_data2),
.out_data3(shiftmux_out_data3),
.out_data4 (shiftmux_out_data4),
.out_resp1 (shiftmux_out_resp1),
.out_resp2(shiftmux_out_resp2),
.out_resp3 ( shiftmux_out_resp3),
.out_resp4 ( shiftmux_out_resp4),
.out_tag1 ( shiftmux_out_tag1),
.out_tag2 ( shiftmux_out_tag2),
.out_tag3 ( shiftmux_out_tag3),
.out_tag4 ( shiftmux_out_tag4),
.prio_alu_out_vld ( prio_shift_out_vld),
.prio_alu_tag ( prio_shift_tag),
.reset ( reset),
.scan_in ( scan_ring7),
.scan_out ( scan_ring8) );
// ===== instantiation for assertions ================
assertion assertion_inst(
.out_resp1(the_bus1.out_resp1),
.out_resp2(the_bus2.out_resp2),
.out_resp3(the_bus3.out_resp3),
.out_resp4(the_bus4.out_resp4),
.c_clk(c_clk),
.req1_cmd_in(the_bus1.req1_cmd_in),
.req2_cmd_in(the_bus2.req2_cmd_in),
.req3_cmd_in(the_bus3.req3_cmd_in),
.req4_cmd_in(the_bus4.req4_cmd_in),
.req1_data_in(the_bus1.req1_data_in),
.req2_data_in(the_bus2.req2_data_in),
.req3_data_in(the_bus3.req3_data_in),
.req4_data_in(the_bus4.req4_data_in),
.out_data1(the_bus1.out_data1),
.out_data2(the_bus2.out_data2),
.out_data3(the_bus3.out_data3),
.out_data4(the_bus4.out_data4)
);
endmodule
========================cal_program.sv ==========================
program cal_program(
input logic c_clk,
output logic reset,
output logic[0:3] req1_cmd_in, req2_cmd_in, req3_cmd_in,
req4_cmd_in,
output logic[0:1] req1_tag_in, req2_tag_in, req3_tag_in,
req4_tag_in,
output logic[0:31] req1_data_in, req2_data_in, req3_data_in,
req4_data_in,
input logic[0:31] out_data1, out_data2, out_data3, out_data4,
input logic[0:1] out_resp1, out_resp2, out_resp3, out_resp4,
out_tag1, out_tag2, out_tag3, out_tag4
);
timeunit 1ns;
timeprecision 1ps;
import cal_package::*;
//clocking block
clocking cb @(negedge c_clk);
default input #1step output #1ns;
input out_data1, out_data2, out_data3, out_data4;
input out_resp1, out_resp2, out_resp3, out_resp4, out_tag1,
out_tag2, out_tag3, out_tag4;
output reset;
output req1_cmd_in, req2_cmd_in, req3_cmd_in, req4_cmd_in;
output req1_tag_in, req2_tag_in, req3_tag_in, req4_tag_in;
output req1_data_in, req2_data_in, req3_data_in, req4_data_in;
endclocking
initial begin
reset <= 1;
req1_cmd_in <= 0;
req1_data_in <= 0 ;
req1_tag_in <= 0;
req2_cmd_in <= 0;
req2_data_in <= 0;
req2_tag_in <= 0;
req3_cmd_in <= 0;
req3_data_in <= 0;
req3_tag_in <= 0;
req4_cmd_in <= 0;
req4_data_in <= 0;
req4_tag_in <= 0;
#600 //ADD command
cb.reset <= 0;
build_P1_cmd(4'b1,2'b1,32'd10);
build_P2_cmd(4'b1,2'b1,32'd100000);
build_P3_cmd(4'b1,2'b1,{{30{1'b1}}, 1'b0});
build_P4_cmd(4'b1,2'b1,{{20{1'b1}}, 1'b0});
#200 //800ns
build_P1_cmd(4'b0,2'b0,32'd25);
build_P2_cmd(4'b0,2'b0,32'd200000);
build_P3_cmd(4'b0,2'b0,32'd2);
build_P4_cmd(4'b0,2'b0,32'd5);
#200 //SUB command 1000ns
build_P1_cmd(4'd2,2'd2,32'd5);
build_P2_cmd(4'd2,2'd2,32'd10);
build_P3_cmd(4'd2,2'd2,32'd50000);
build_P4_cmd(4'd2,2'd2,{31{1'b1}});
#200 //1200ns
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
#200//ADD command 1400ns
build_P1_cmd(4'b1,2'd3,32'b111110000011111000001111100000);
build_P2_cmd(4'b1,2'd3,32'b1011);
build_P3_cmd(4'b1,2'd3,32'b111100011);
build_P4_cmd(4'b1,2'd3,32'b100000000001);
add_checker(32'd10,32'd25,out_data1); //out_data1 should be 35
#200 //1600ns
build_P1_cmd(4'b0,2'b0,32'b000001111100000111110000011111);
build_P2_cmd(4'b0,2'b0,32'b1001);
build_P3_cmd(4'b0,2'b0,32'b11100011);
build_P4_cmd(4'b0,2'b0,32'b10);
add_checker(32'd100000,32'd200000,out_data2);//out_data2 should be
3000000
sub_checker(32'd5,32'd5,out_data1); //out_data1 should be 0
#200 //ADD 1800ns
build_P1_cmd(4'b1,2'b0,32'b100);
build_P2_cmd(4'b1,2'b0,32'b1000);
build_P3_cmd(4'b1,2'b0,32'b10000);
build_P4_cmd(4'b1,2'b0,32'b100000);
add_checker({{30{1'b1}}, 1'b0},32'd2,out_data3);
#200 //2000ns
build_P1_cmd(4'b0,2'b0,32'b100);
build_P2_cmd(4'b0,2'b0,32'b1000);
build_P3_cmd(4'b0,2'b0,32'b10000);
build_P4_cmd(4'b0,2'b0,32'b100000);
add_checker({{20{1'b1}}, 1'b0},32'd5,out_data4);
#200//SUB 2200ns
build_P1_cmd(4'd2,2'b1,32'd5);
build_P2_cmd(4'd2,2'b1,32'd10);
build_P3_cmd(4'd2,2'b1,32'd50000);
build_P4_cmd(4'd2,2'b1,{31{1'b1}});
sub_checker({31{1'b1}},{31{1'b1}},out_data4);
#200 //2400ns
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
sub_checker(32'd10,32'd9,out_data2);
#200 //ADD 2600ns
build_P1_cmd(4'b1,2'd2,32'd5);
build_P2_cmd(4'b1,2'd2,32'd10);
build_P3_cmd(4'b1,2'd2,32'd50000);
build_P4_cmd(4'b1,2'd2,{31{1'b1}});
sub_checker(32'd50000,32'd1999,out_data3);
#200
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
#200 //SHIFT LEFT
build_P1_cmd(4'd5,2'd3,32'b1111);
build_P2_cmd(4'd5,2'd3,32'b1010101);
build_P3_cmd(4'd5,2'd3,{{30{1'b1}}, 1'b0});
build_P4_cmd(4'd5,2'd3,{{20{1'b1}}, 1'b0});
#200
build_P1_cmd(4'b0,2'b0,32'd2);
build_P2_cmd(4'b0,2'b0,32'd5);
build_P3_cmd(4'b0,2'b0,32'd20);
build_P4_cmd(4'b0,2'b0,32'd32);
#200 //ADD
build_P1_cmd(4'b1,2'd2,32'd5);
build_P2_cmd(4'b1,2'd2,32'd10);
build_P3_cmd(4'b1,2'd2,32'd50000);
build_P4_cmd(4'b1,2'd2,{31{1'b1}});
#200
build_P1_cmd(4'b0,2'b0,32'd5);
build_P2_cmd(4'b0,2'b0,32'd9);
build_P3_cmd(4'b0,2'b0,32'd1999);
build_P4_cmd(4'b0,2'b0,{31{1'b1}});
#200 //SHIFT RIGHT
build_P1_cmd(4'd6,2'b0,{31{1'b1}});
build_P2_cmd(4'd6,2'b0,32'b111100001111);
build_P3_cmd(4'd6,2'b0,32'b101010);
build_P4_cmd(4'd6,2'b0,{15{1'b1}});
#200
build_P1_cmd(4'b0,2'b0,32'd2);
build_P2_cmd(4'b0,2'b0,32'd4);
build_P3_cmd(4'b0,2'b0,32'd20);
build_P4_cmd(4'b0,2'b0,32'd32);
shl_checker(32'b1111,32'd2,out_data1);
#200 //shift left
build_P1_cmd(4'd5,2'b1,32'b1011011101111);
build_P2_cmd(4'd5,2'b1,32'b1111110000011);
build_P3_cmd(4'd5,2'b1,32'b1010011100100);
build_P4_cmd(4'd5,2'b1,32'b100101010101);
shl_checker(32'b1010101,32'd4,out_data2);
#200
build_P1_cmd(4'b0,2'b0,32'd2);
build_P2_cmd(4'b0,2'b0,32'd5);
build_P3_cmd(4'b0,2'b0,32'd15);
build_P4_cmd(4'b0,2'b0,32'd20);
shl_checker({30{1'b1}},32'd20,out_data3);
#200 //shift right
build_P1_cmd(4'd6,2'd2,{31{1'b1}});
build_P2_cmd(4'd6,2'd2,{25{1'b1}});
build_P3_cmd(4'd6,2'd2,{ {10{1'b1}},{10{1'b0}},{10{1'b1}} });
build_P4_cmd(4'd6,2'd2,{5{1'b1}});
shl_checker({{20{1'b1}}, 1'b0},32'd32,out_data4);
#200
build_P1_cmd(4'b0,2'b0,32'd10);
build_P2_cmd(4'b0,2'b0,32'd20);
build_P3_cmd(4'b0,2'b0,32'd29);
build_P4_cmd(4'b0,2'b0,32'd3);
#600
shr_checker({31{1'b1}},32'd10,out_data1);
#200
shr_checker({25{1'b1}},32'd20,out_data2);
#200
shr_checker({{10{1'b1}},{10{1'b0}},{10{1'b1}}},32'd29,out_data3);
#200
shr_checker({5{1'b1}},32'd3,out_data4);
#2000 $stop;
end
// initial begin
// ====================================== checker
===================================//
task add_checker(input[31:0]operand1,operand2,sum);
begin
reg[31:0] expected;
logic[15:0] add_error_num=0;
expected = operand1+operand2;
if(expected!==sum)
begin
$display("add error",$time);
add_error_num++;
$display("ADD error numbers are", add_error_num);
end
end
endtask
task sub_checker(input[31:0]operand1,operand2,sub);
begin
reg[31:0] expected;
logic[15:0] sub_error_num=0;
expected = operand1-operand2;
if(expected!==sub)
begin
$display("sub error",$time);
sub_error_num++;
$display("SUBTRACT error numbers are", sub_error_num);
end
end
endtask
//
task shl_checker(input[31:0]operand1,operand2,shl);
begin
reg[31:0] expected;
logic[15:0] shl_error_num=0;
expected = operand1 << operand2;
if(expected!==shl)
begin
$display("shift left error",$time);
shl_error_num++;
$display("SHIFT_LEFT error numbers are", shl_error_num);
end
end
endtask
task shr_checker(input[31:0]operand1,operand2,shr);
begin
reg[31:0] expected;
logic[15:0] shr_error_num=0;
expected = operand1 >> operand2;
if(expected!==shr)
begin
$display("shift right error",$time);
shr_error_num++;
$display("SHIFT_RIGHT error numbers are", shr_error_num);
end
end
endtask
//====================== function to generate expected
results ===============//
function [32:0] gen_expected_result;
input [3:0] cmd;
input [0:31] op1, op2;
case(cmd)
ADD:gen_expected_result= op1 + op2;
SUBTRACT:gen_expected_result= op1 - op2;
SHIFT_LEFT: gen_expected_result= op1<<op2;
SHIFT_RIGHT: gen_expected_result= op1>>op2;
default: gen_expected_result= 32'b0;
endcase
endfunction
//========================= build valid command
task build_P1_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req1_cmd_in <= cmd;
cb.req1_data_in <= operand;
cb.req1_tag_in <= tag;
endtask
task build_P2_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req2_cmd_in <= cmd;
cb.req2_data_in <= operand;
cb.req2_tag_in <= tag;
endtask
task build_P3_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req3_cmd_in <= cmd;
cb.req3_data_in <= operand;
cb.req3_tag_in <= tag;
endtask
task build_P4_cmd;
input [3:0] cmd;
input [2:0] tag;
input[31:0] operand;
logic[31:0] expected;
cb.req4_cmd_in <= cmd;
cb.req4_data_in <= operand;
cb.req4_tag_in <= tag;
endtask
endprogram
======================cal_package.sv====================
package cal_package;
typedef enum {
ADD,
SUBTRACT,
SHIFT_RIGHT,
SHIFT_LEFT,
INVALID
} cmd;
// structs for building valid command
//
typedef struct {
int add_max;
int add_ofl1;
int add_rand;
int sub_equ;
int sub_ufl1;
int sub_rand;
int shl_min;
int shl_max;
int shl_rand;
int shr_min;
int shr_max;
int shr_rand;
} cmd_type;
endpackage
==========================APB_intf.sv
interface apb();
logic[0:3] req1_cmd_in,req2_cmd_in,req3_cmd_in,req4_cmd_in;
logic[0:31] req1_data_in,req2_data_in,req3_data_in,req4_data_in;
logic[0:1] req1_tag_in,req2_tag_in,req3_tag_in,req4_tag_in;
logic[0:1] out_resp1,out_resp2,out_resp3,out_resp4;
logic[0:31] out_data1,out_data2,out_data3,out_data4;
logic[0:1] out_tag1,out_tag2,out_tag3,out_tag4;
//--------------------------------- Mod ports
---------------------------------------//
// These go to DUT
modport one (output out_resp1, out_data1, out_tag1,
input req1_cmd_in, req1_data_in, req1_tag_in);
modport two (output out_resp2, out_data2, out_tag2,
input req2_cmd_in, req2_data_in, req2_tag_in);
modport three (output out_resp3, out_data3, out_tag3,
input req3_cmd_in, req3_data_in, req3_tag_in);
modport four (output out_resp4, out_data4, out_tag4,
input req4_cmd_in, req4_data_in, req4_tag_in);
// This comes from test bench
modport tb (output req1_cmd_in, req1_data_in, req1_tag_in,
req2_cmd_in, req2_data_in, req2_tag_in,
req3_cmd_in, req3_data_in, req3_tag_in,
req4_cmd_in, req4_data_in, req4_tag_in,
input out_resp1, out_data1, out_tag1,
out_resp2, out_data2, out_tag2,
out_resp3, out_data3, out_tag3,
out_resp4, out_data4, out_tag4
);
// inputs (outputs from DUT) to the Test bench and outputs (inputs to
the DUT)from Test bench.
endinterface:apb
=========================================