clarification

[srinu]

in verilog i defined some memory.For my application i want to load
image in to that memory directly.Is it possible in verilog?
if it is possible is it synthesizable or not?
example:
reg [7:0]memr[0:63][0:63];
reg [7:0]memry[0:4095];
$readmemh("128.txt",memry,0,4095);
for(i=0;i<=63;i=i+1)
for(j=0;j<=63;j=j+1)
begin
memr[j]=memry[l];
l=ltemp+1;
ltemp=l;
end
in this code 128.txt is the text file which is having image
pixels.this code is not synthesizing.
so any one having altenative for this code please help me in this
regard.

 

[Jonathan Bromley]

On Fri, 16 Nov 2007 20:08:06 -0800 (PST), srinu <srinu.bkn@gmail.com>
wrote:

;
reg [7:0]memry[0:4095];
$readmemh("128.txt",memry,0,4095);
for(i=0;i<=63;i=i+1)
for(j=0;j<=63;j=j+1)
begin
memr[j]=memry[l];
l=ltemp+1;
ltemp=l;
end
in this code 128.txt is the text file which is having image
pixels.this code is not synthesizing.
so any one having altenative for this code please help me in this
regard.

You are asking the synthesis tool to do several
impossible things before breakfast:
* $readmemh - most synth tools can't build ROMs from $readmemh
* copying all 4096 elements from memry[] to memr[][] in a
single copy operation - can you kindly explain what kind
of hardware you think that represents?
If you say more about what you're really trying to do,
you may get some more specific suggestions. Right now
I can't begin to imagine what sort of design you are
attempting to create.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[mk]

On Fri, 16 Nov 2007 20:08:06 -0800 (PST), srinu <srinu.bkn@gmail.com>
wrote:

in verilog i defined some memory.For my application i want to load
image in to that memory directly.Is it possible in verilog?
if it is possible is it synthesizable or not?
example:
reg [7:0]memr[0:63][0:63];
reg [7:0]memry[0:4095];
$readmemh("128.txt",memry,0,4095);
for(i=0;i<=63;i=i+1)
for(j=0;j<=63;j=j+1)
begin
memr[j]=memry[l];
l=ltemp+1;
ltemp=l;
end
in this code 128.txt is the text file which is having image
pixels.this code is not synthesizing.
so any one having altenative for this code please help me in this
regard.

$readmemh works because it's a part of your simulator which runs on
your PC which has a hard disk where the file resides and the OS knows
how to access that file so $readmemh can get to it. Think about how
this can possibly work in a synthesized design. You need to duplicate
all these features ie you need some external storage, you need to be
able to name a section of the storage (ala the file name but could be
an address and a range) and you need to get those bytes from the
external storage into the memory in your design.
To make the long story short, $readmemh is not synthesizable. The
easiest replacement is exposing the address & data interfaces of your
memory to your design's top level and generating write transactions
there so that the synthesized design can be acted upon the same way.

 

[John_H]

srinu wrote:

in verilog i defined some memory.For my application i want to load
image in to that memory directly.Is it possible in verilog?
if it is possible is it synthesizable or not?
example:
reg [7:0]memr[0:63][0:63];
reg [7:0]memry[0:4095];
$readmemh("128.txt",memry,0,4095);
for(i=0;i<=63;i=i+1)
for(j=0;j<=63;j=j+1)
begin
memr[j]=memry[l];
l=ltemp+1;
ltemp=l;
end
in this code 128.txt is the text file which is having image
pixels.this code is not synthesizing.
so any one having altenative for this code please help me in this
regard.

You obviously need to communicate which synthesizer you're using. I was
disappointed that SynplifyPro supports $redmem (of the various type) for
single-dimensional memories but not multi-dimensional memories. The
code I produced was similar to yours, I just used a multi-dimensional
wire to assign the reg array to something I can work with more readily.
Caution: I haven't run mine all the way through synthesis to verify my
memory image is complete just yet.

Change memr to a multi-dimensional wire array and use generates to make
the assignments. There's no hardware issue as suggested by another
poster because the wire array is just another way to access the 1-D memory.

- John_H